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The recent spectacular progress in modern Nan electronic technology enabled implementation of very complex multiprocessor systems on single chips (MPSoCs) and created a big stimulus towards development of MPSoCs for embedded applications. The increasingly complex MPSoCs are required to perform real-time computations to extremely tight schedules and to satisfy high demands regarding adaptability, as...
Significant advances in the field of configurable computing have enabled parallel processing within a single Field-Programmable Gate Array (FPGA) chip. This paper presents the implementation of a flexible and programmable Single Instruction Multiple Data (SIMD) processing system on FPGA that can be adapted to the application. Its implementation is based on an IP (Intellectual Property) assembling...
Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation...
The Multi-core Video Analytics Engine (MVE??) is an easily configurable, compact, high-performance processing architecture that can be used to implement complete video analytics solutions in a single FPGA embedded in intelligent surveillance cameras. With the steadily growing demand for increased processing power at lower costs for video analytics systems, especially intelligent cameras with embedded...
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise,...
Multicore environments are rapidly emerging and are widely used in SoC, but accompanying parallelism programming and debugging impact the ordinary sequential world. Unfortunately, according to Heisenberg's uncertainty principle, the instrument trying to probe the target will cause probe effects. Therefore, current intrusive debugging methodologies for sequential programs cannot be used directly in...
In this paper, a functional model of SystemC-based MPEG-2 decoder is presented, which is of heterogeneous multi-IP-cores and hybrid-interconnections. Considering the application-specific features into the design flow, three important aspects are analyzed, including function partition, parameter sharing, and interconnection topology, which are the key technical difficulties in the system level design...
The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the higher level of abstraction, we implement a...
Stream processor, Inc. (SPI) has introduced the Storm-1 stream processing system-on-a-chip (SoC) which contains 16 data-parallel processing arrays with five very long instruction word (VLIW) arithmetic logic units (ALUs) in each lane (altogether 80 processing units). In the paper the implementation of emulated-digital cellular neural networks universal machine (CNN-UM) simulation kernel on the Storm-1...
Single instruction multiple data processors are increasingly used in embedded systems for multimedia applications because of their area and energy-efficiency. Neighboring communications between the processing elements are a key issue in SIMD processors. They are present in most data parallel applications. However, the lack of flexibility in major parallel architectures is its main shortcoming. In...
This paper presents a system level design flow which enables rapid design space exploration and a verification tool to assist a designer to identify an FPGA-based MPSoC for stream-oriented application. The case study, JPEG encoding, illustrates how the tool exploits the task-level parallelism and produces a suitable architectural design, binding and scheduling algorithm while satisfying physical constraints.
As the size, hardware complexity, and programming diversity of parallel systems continue to evolve, the range of alternatives for implementing a task on these systems grows. Choosing a parallel algorithm and implementation becomes an important decision, and the choice has a significant impact on the execution time of the application. This paper focuses on the implementation of a SIMD parallel reduction...
A current trend in digital signal processing is to reduce power and energy consumption. The use of asynchronous designs is one of the possible ways to achieve these goals, but the nature of these circuits requires different modeling schemes. We present in this paper our own model for a novel DSP architecture comprising multiple asynchronous cores and ALUs per core. Our approach shows how to match...
Transport triggered architecture (TTA) is one kind of application-specific instruction processors (ASIP), which fits embedded systems and offers a cost-effective trade-off between the energy-efficiency and performance. However its architecture and very long instruction word (VLIW) are alike, which also results in a very poor code density. In embedded systems, memory is one of the most expensive resources...
We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus,...
iVisual, an intelligent visual sensor SoC integrating 2790fps CMOS image sensor and 76.8GOPS, 374 mW vision processor, is implemented on a 7.5 mm times 9.4 mm die with 0.18 mum CIS process. The light-in, answer-out SoC architecture avoids privacy problems of intelligent visual sensor. The feature processor and inter-processor synchronization scheme together increase 51% of average throughput. The...
In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology with the (parallelized) application mapped onto it in only a matter of hours. During this traversal, which offers a high degree of automation, guidance is provided by Daedalus' integrated system-level design space exploration...
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