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Most of the applications require hard real time signal/data processing potentiality for which fast and dedicated VLSI architectures are the best solution. But designing such circuits lead to high occurrences of failure in the system. Hence there is a critical need for fault tolerance techniques for VLSI designs to increase the reliability of the system. Redundancy techniques are implemented widely...
Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work...
Due to aggressive scaling, reliability issues influence the design process of integrated circuits more and more. A well known technique to tackle these issues represents Triple Modular Redundancy (TMR). It strongly improves reliability of a design at the expense of at least tripled area and power consumption. In this contribution, we propose an enhanced TMR approach that significantly decreases the...
We consider systems comprised of multiple triple modular redundancy (TMR) units in series. Only recently have researchers found that even such simple systems can be configured into various structures. We develop an algorithm for finding a structure that maximizes reliability. Using this algorithm we show that new structures have optimal reliability within some ranges of voter and module reliability.
Nanoelectronic systems are extremely likely to demonstrate high defect and fault rates. As a result, defect and/or fault tolerance may be necessary at several levels throughout the system. Methods for improving defect tolerance, in order to prevent faults, at the component level for QCA have been studied. However, methods and results considering fault tolerance in QCA have received less attention...
In this paper, a methodology is presented to perform automatic selective TMR insertion on digital circuits, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared with TMR.
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
This paper presents an efficient high-level synthesis (HLS) approach to improve RT-level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-level controller to locate the faults. The fault detection step is...
In this paper, we propose a distributed voting strategy to design a robust NMR system. We show that using inexpensive current-based drivers and buffers, we can completely eliminate the centralized voter unit and do the majority voting among N modules in a distributed fashion. Our strategy achieves high reliability that is vital for future nano systems in which high defect rate is expected. Experimental...
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