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In this paper, a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally demonstrated. The technology is based on a micro-meter level lithography equipment, that is, it does not need any critical photolithographic step. The masking layer for fin formation is the nitride caped oxide layer which is reduced in width from sub-micrometer scale to nano-meter scale through...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Assited by Co as catalyst, an interesting structure, dandelion-shaped SiCN rods, was synthesized using microwave plasma chemical vapor deposition method with gas mixtures of CH4, H2 and N2 as precursors and Si chips inserted in the sample holder at symmetrical positions around the specimen as additional Si sources. Scanning electron microscopy shows each rod has not only a column about 0.4~0.8 mum...
We present a simple method to fabricate large area of silicon nanowires array with low-cost and throughput by a catalytic electrochemical etching process. In our experiment, a thin layer of polyelectrolyte (PAH) was used to absorb negatively charged PS sphere. Using the PS sphere as mask, the silicon nanowires arrays were fabricated by a silver catalytic electrochemical etching process. By SEM and...
Investigations on the piezoresistive effect of poly-silicon nanofibns (PSNFs) have not been presented, since it is considered that their piezoresistive properties can become worse with film thickness decreasing. However, our experimental results indicated that the PSNFs (~100nm in thickness, even thinner) had a high gauge factor (>30) and low temperature coefficients of resistance and gauge factor,...
The composite structure of silicon tips and vertical aligned carbon nanotubes (CNTs) was prepared using plasma enhanced hot filament chemical vapor deposition (PE-HFCVD) method on the silicon wafer, and Au/Ni film coated on the substrate was considered as a catalyst. High proportion hydrogen of 96% volume percentage and high total pressure are used during preparing process, and the pure CNTs, pure...
This paper presents lateral growth of carbon nanotube (CNT) between two electrodes and its use as nano temperature sensor. Fabrication of electrodes is made by MEMS techniques. The CNT is grown selectively by microwave plasma chemical vapor deposition between two electrodes. After wire bonding, the grown CNT is tested and calibrated. The growth conditions of CNT, such as the flow rate of CH4 or N2...
We have proposed batch fabrication of silicon pyramids with upward CNTs on the tips at one time by a chemical vapor deposition (CVD) process. To synthesize upward CNTs on the pyramid tips, an upward electric field was applied to the silicon pyramid array during the CVD process. By electric field simulation and verifying experiment on silicon one-dimensional array structures, we found that CNTs tended...
It is well known that porous silicon (PS) has a large range of morphologies. A pulsed anodic etching method is developed to fabricate uniform PS with different surface morphologies. Changes of PS on n-type Si surface after anodization with pulsed current with varying delay time were studied by scanning electron microscopy (SEM) and Raman spectroscopy. The SEM images show that a uniform and well defined...
In this study, the deformation behavior of single-crystal Si (100) was examined using nanoindentation, followed by analysis using cross-sectional transmission electron microscopy (XTEM), scanning electron microscopy (SEM), and Raman microspectroscopy. XTEM samples were prepared by focused ion beam (FIB) milling to accurately position the cross-section through the indentations. The deformation via...
Au-Ag nanoparticles are used as nanomasks for Si nanowires fabrication. Au-Ag alloy film deposited on Si substrate is annealed in H 2 ambient at a temperature of 750degC. The SiNWs were fabricated through a dry etching processing in an inductively coupled plasma (ICP) system. SEM images of the uniform vertically aligned silicon nanowire arrays show 50 to 100 nm nanowire diameter range and ~1.1 mum...
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