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CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications...
CMOS utilizing high mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for low power advanced LSIs in the future, because of the expectation of high current drive. In addition, Tunneling-FET (TFET) using III–V/Ge-based materials can also be one of the important device families with steep slope device switching, which is mandatory for the ultra-low power devices...
The use of high mobility channel materials such as Germanium can increase the pMOSFET drive current, thus improving the switching speed of CMOS. In this study the impact of the lateral spacer thickness on the performance of a 20 nm gate-length implant-free quantum well (IFQW) Ge pMOSFET is investigated using comprehensive full-band Monte Carlo simulations. The results of these simulations show that...
Nanowire MOSFETs have been recognized as one of the possible choices to continue the scaling of CMOS beyond conventional scaling limits. In present study we study various aspects of device characteristics and Mixedmode circuit behavior of Silicon and Germanium Nanowire MOSFETs. The various parameters determining the behavior of device in the analog/digital circuits is studied and compared for Nanowire...
We have systematically investigated Ge interface passivation methods, and the highest electron (1920 cm2/Vs) and hole mobility (725 cm2/Vs) have been demonstrated by dramatic reduction of Dit through the collaboration of self-passivation and valency passivation. In Si passivation, it is found that Si contributes to the upper half (worse) and lower one (better) in the bandgap differently. This study...
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quality single crystal Ge selectively grown heteroepitaxially on Si using Multiple Hydrogen Anealing for Heteroepitaxy(MHAH) technique. Until now low source/drain series resistance in Ge n-MOSFETs has been a highly challenging problem. Source and drain are formed by implant-free, in-situ doping process for...
We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k...
Germanium has emerged as an exciting alternative material for high-performance scaled CMOS, however not without difficulties. After a review of the state-of-the-art, mainly focusing on two techniques to passivate the channel/dielectric interface, we analyze the strengths (carrier mobility, band gap), and weaknesses (n-type doping, lattice mismatch and BTBT leakage) of Ge for MOSFETs. We also identify...
In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect...
Prospects of velocity enhancement as the main driver of performance scaling in future CMOS are examined. Limits of velocity enhancement in uniaxially strained Si are first presented and then outlooks of novel channel materials such as Ge and III-V semiconductors are discussed. Finally, characteristics of performance scaling under power dissipation constraints are studied.
In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials have to be created. A channel material with high mobility and therefore high injection velocity can increase on current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This paper presents simulations on tunnel field-effect transistors (TFET) and comparisons carefully to assess their impact at the same supply voltage. Current-voltage characteristics are simulated for n and p TFETs with different channel materials:Si,Ge,InGaAs, and InAs. Results show that InAs has the highest current for its smallest bandgap and effective mass, but it can not meet the off-state leakage...
Meeting performance targets of 22 nm Si- CMOS and beyond, as per 2006 ITRS update, will require innovation at all levels of CMOS development, including new channel materials, device design, integration, circuit design, and system architecture. In new channel materials, some of the options under consideration include (a) local and global strain, (b) Si surface orientation, and (c) non-Si materials...
Tensile-strained Ge photodetector is realized on Si-substrate using novel SiSiGe compliant layer with two-step Ge-process. Monolithic integration of p-i-n detectors with low dark current (0.4 nA), responsivity (190 mA/W) and high speed (5 GHz) on Ge-CMOS platform is demonstrated, with Ge pMOSFET showing 2X Si hole mobility.
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