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A RF leakage phenomenon in GaN HEMTs on Si substrates is analyzed with taking atomic diffusion at buffer/substrate interface into consideration, and a novel physical model of RF leakage based on the analysis is proposed. The Al or Ga atoms are moved from buffer layer to Si substrate at an epitaxial growth. Then, an acceptor layer with high hole density and an inversion layer with high electron density...
This paper presents the design exploration of a basic cascode circuit (CAS) targeted to increase the intrinsic gain Aν of a graphene field-effect-transistor (GFET) by decreasing its output conductance go. First, the parameters of a large-signal compact-model, based on drift-diffusion carrier transport, are fit to measurements carried on 2 CVD GFETs, fabricated independently by different research groups...
In this paper, the equivalent circuit model of a pair of TSVs in a passive interposer base is developed, with the nonlinear MOS capacitance effect treated appropriately. Based on the circuit model, the transient analysis of the interposer TSVs is carried out. The results would be helpful for the design and practical applications of interposer-based 2.5-D IC systems.
Crosstalk between the interconnects cause serious electromagnetic interference (EMI). The high density interconnects, including redistribution layers (RDLs) and through-silicon-vias (TSVs) in silicon interposer, require effective crosstalk-reduction signaling schemes. In this paper, a novel co-planar waveguide (CPW) RDL structure, where the ground lines directly contact the silicon substrate without...
A high efficient CMOS class-E power amplifier (PA) by using Quad Flat No-leads (QFN) package combined with Through Silicon Via (TSV) grounding is presented. TSV has much smaller parasitic inductance and resistance than wire-bonds. TSV technology can improve PA efficiency, reduce die size samples and retain low cost in QFN package. The TSV samples are made and measured by using double-side probing...
This paper presents a 3D circuit model capable of rapidly and accurately evaluating substrate noise coupling in the context of 3D integration. Since TSVs are large and noisy structures, the evaluation of electromagnetic coupling to and from TSVs has become crucial to the design of threedimensional integrated circuits. In this work, we present a fast and accurate 3D circuit model to this end. The model...
In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.
An equivalent circuit model of through silicon via considering the eddy current flow inside the silicon is proposed to predict the electrical performance up to 100GHz. The parasitic elements of the proposed circuit model are derived by the structural dimensions and material properties of the TSV, and its electrical performance of the proposed equivalent circuit model is analyzed with structure size...
Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through silicon vias (TSVs) are proposed. The expressions are functions of the geometric and material parameters of TSVs. They also can be applied to the cylindrical TSVs when the slope angle is zero. The two parasitic capacitances increase as the slope angle increases, which implies that the tapered...
In this paper, a systematic test approach is presented for rapid detection of the defects in pre- and post-bond through-silicon vias (TSV). The cylindrical, annular, and coaxial TSVs are studied using the full-wave electromagnetic simulation. The impacts of open and pinhole defects in the pre-bond TSVs can be effectively observed in the Z-parameter variation. Then, a defect detection scheme is developed...
A laser bonding technique has been developed recently to create an innovative material based on a silicon/diamond interface. In this work, we propose the development and the application of a numerical model for TCAD simulations of poly-crystalline diamond conceived for Silicon-on-Diamond (SoD) sensors to be used, e.g., as particle detectors in High Energy Physics (HEP) experiments. The model is based...
This paper looksat the impact of consideringthe exact or approximated values for the nonlinear depletion capacitance in a TSV equivalent circuit for transient analysis. Furthermore, the effects of the time variant and nonlinear behavior of the doped bulk silicon substrate on signal propagation and crosstalk are also studied.
The characterization on coupling effect of on-chip octagon spiral inductors has been presented. The coupling effects in different parted distances are presented. And the relationship between the coupling and the distance is plotted and discussed. What's more, a practical design tip about the distance of adjacent inductors is presented. Finally, the predominant role of coupling effect is investigated...
This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically...
Through silicon via (TSV) based 3D-IC is the key technology to satisfy the continuously growing demand on lower power consumption, higher system bandwidth and smaller form factor of electronic devices. As the I/O count increases up to the order of tens of thousands for high speed data transmission, TSV diameter and interconnection pitch are reduced, which may cause various defects throughout the channel...
This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic transformers on silicon substrates. R, L Foster networks in a T-topology are used to capture the frequency-dependent proximity and skin effects in the transformer windings as well as substrate eddy-current effects and, hence, the complete frequency-dependent self and mutual impedances of the transformer. The...
With the development of the integrated circuits, the electronic devices become smaller and smaller, higher density within, and more and more function. The through silicon via (TSV) is the core to the three-dimensional integrated circuit. This paper focuses on the effect to the transmission characteristic of the Ground-Signal-Ground (GSG) TSV. Effects of design parameters, co-simulation with CPW, equivalent...
With the development of the integrated circuits, the electronic devices become smaller and smaller, higher density within, and more and more function. The through silicon via (TSV) is the core to the three-dimensional integrated circuit. This paper focuses on the effect to the transmission characteristic of the Ground-Signal-Ground (GSG) TSV. Effects of design parameters, co-simulation with CPW, equivalent...
CPW lines on a 0.015 0-cm resistivity silicon substrate are simulated using HFSS. The electric field distribution from HFSS is analyzed to demonstrate that silicon substrate loss plays an important role and cannot be ignored. A novel physics-based model is developed to predict the characteristics of the CPWs and compared with measured data. A good agreement is obtained up to 110 GHz and demonstrates...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
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