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Recent studies show that increasing numbers of design bugs are escaping to post-silicon due to the complexity of advanced designs and the lack of adequate verification tools that can validate complex electrical interactions between electrical subsystems on an integrated circuit. In this paper, we present a novel tool for post-silicon validation of mixed-signal/RF circuits through cooperative test...
A new production ready compact model for future FinFETs is presented. This single unified model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. New mobility models support Ge p-FinFETs and InGaAs n-FinFETs. A new quantum effects model enables accurate modeling of III–V FinFETs. Special attention is paid to shape agnostic short-channel effect...
Measuring head impacts in helmeted sports is important for prognosticating onset of mild traumatic brain injuries (MTBIs) or concussions. In this paper we present a miniature battery-less, self-powered sensor that can be embedded inside sport helmets and can continuously monitor and log the statistics of different levels of helmet impacts. At the core of the proposed sensor is a novel time-dilation...
Evaluation of novel devices in a circuit context is crucial to identifying and maximizing their value. We propose a new framework, PROCEED, and metrics for accurate device-circuit co-evaluation through proper optimization of digital circuit benchmarks. PROCEED assesses technology suitability over a wide operating region (MHz to GHz) by leveraging available circuit knobs (Vt assignment, power management,...
In this paper, practical test patterns are designed to calculate the characteristics of Through-Silicon Via (TSV) pairs in a silicon interposer. Proposed test patterns include probing pads, traces and TSVs, which are modeled by a combination of impedances and admittances. Performance of the test patterns is obtained from simulation models built in full wave simulation solver. TSV response is then...
This paper presents the methodology to obtain the snapback curves and second breakdown point of an ESD stressed device through TCAD simulation. This method allows an excellent ESD simulation convergence and then good ESD prediction with a significantly reduced computation time. One 0.5um CMOS technology has been simulated for experimental support.
The co-existence of two different sets of parameter definitions, requirements and specifications in the domain of digital system design; namely the time domain (TD) and frequency domain (FD), is imposing some challenges on digital system design. Those challenges are increasing with the increase in system speed and are hard to address using traditional methods. This paper proposes a new methodology...
GaN devices have significant advantages in power density, thermal characteristics, and voltage range over those based on conventional compound semiconductors or Silicon. With GaN, as in other materials systems there are significant advantages in cycle time and strength of design from use of TCAD. Here TCAD simulations of AlGaN/GaN HEMTs are shown to accurately match measured DC and small signal AC...
This paper deals with noise distribution over nonuniform two-dimensional planes of multi-core CPU packages. The numerical algorithm is based on circuit finite difference time domain, which employs voltage-controlled current sources in the current/voltage updating scheme. It is applied to plane pairs with non-uniform geometry (which can include metal voids), as well as arbitrary location of sources...
The paper deals with three-phase AC/AC frequency converter. Implementation of the current source matrix converter (CSMC) with space vector modulation (SVM) is presented. The specialized DSP and FPGA cards are used in the control circuit realization. Experimental test results of ca 1 kVA laboratory model are presented to confirm of the discussed CSMC properties.
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
A medium power (80V, 50A pulsed) Silicon double thyristor with turn-on speed of 10ns range has been designed and fabricated. The integrated launching thyristor allows to trigger the device with a low signal of CMOS logic output range, so that the resulting gate turn-on charges are at least a factor of 1000 smaller than the equivalent power MOS transistor gate-control charges. The high tum-on sensitivity...
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