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This paper presents a novel power-constrained algorithmic design methodology for radiofrequency (RF) low-noise amplifiers (LNAs). The methodology is based on matrix descriptions of the transistors allowing for the first time the derivation of exact synthesis equations for input impedance matching and transducer gain optimization. The equations are embedded in an algorithm for design tradeoffs between...
Based on a system-level design methodology and a modified power delivery network model, optimization and benchmarking are performed for a processor implemented with the power-gating technique under various package configurations. Optimal widths of the sleep transistors are obtained based on how frequently the processors need to switch between active and idle state. Up to 75% of the energy-delay product...
Constant input and output mismatch circles in the output load plane are introduced as the basis for low-noise amplifier design methodology. Optimum tradeoff between input and output matching levels results as the application of a design chart providing, at the same time, the corresponding stage transducer gain. The role of degenerative series feedback is studied and systematically embedded in the...
In this paper a very low voltage low power CMOS Low Noise Amplifier (LNA) suitable for ultra low power applications is presented. A new design methodology for noise and power consumption optimization is described. By using forward body bias (FBB), the proposed LNA, implemented in a 0.13μm CMOS process, can operate at 0.5V supply voltage, at 2.4GHz. Post layout simulation results show that it achieves...
This paper presents a new compact and comprehensive design methodology for RF CMOS source degenerated cascode dual functionality low-noise amplifier (LNA) and power amplifier (PA) for the IEEE 802.15.4 standard (commercially known as ZigBee). The proposed design methodology is based on simultaneous graphical visualization of the relationship between all relevant performance parameters and the corresponding...
This paper describes the design of an 8-bit fully differential pipelined analog-to-digital converter (ADC). The design methodology employed in this work follows a technique of allocating appropriate error budgets to the various ADC errors such that the maximum differential nonlinearity (DNL) error is less than 0.5 least significant bits (LSB). Simulation results show that the ADC maximum DNL errors...
This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
In this paper the design methodology of a single stage CMOS low noise amplifier with slow wave transmission lines was described. This design methodology is useful for designing higher gain multi stage amplifiers.
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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