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This paper describes the design of an 8-bit fully differential pipelined analog-to-digital converter (ADC). The design methodology employed in this work follows a technique of allocating appropriate error budgets to the various ADC errors such that the maximum differential nonlinearity (DNL) error is less than 0.5 least significant bits (LSB). Simulation results show that the ADC maximum DNL errors...
Design of a 0.9-V 5-MHz sampling frequency 120-μW 1-bit fourth-order feedforward sigma-delta modulator using a standard CMOS 130-nm technology is presented. Modifications to an OTA design to improve its GBW and slew rate are presented. The simulated GBW and slew rate of the modified OTA have increased to 200 MHz and 15 V/μs, respectively. Consequently, the modulator sampling frequency has increased...
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