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Precision operational amplifiers (opamp) with 30V supply operation have been widely used to support industrial, instrumentation, and other applications [1]. Most of them have been realized with BJT or JFET processes [1] to offer voltage noise PSD better than 10nV/√Hz and offset voltage drift better than 1μV/°C. Recently, opamps with similar specifications have become available using CMOS based processes...
This paper presents a digitally assisted period modulation (PM)-based capacitance-to-digital converter (CDC) that is >9x smaller than prior CDCs with >10b resolution [1-4], and improves the energy efficiency by >10x compared to previous PM-based CDCs [1]. This is achieved with the help of a piece-wise charge transfer technique that eliminates the need for a large on-chip integration capacitor,...
This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption...
Researchers in many advanced R&D and scientific instrumentation fields must analyze high-speed phenomena through the use of high-speed video cameras with over 1Mfps. Conventional image sensors are mainly rolling-shutter continuous CMOS image sensors that repeat exposure and read-out signals quickly for every frame [1]. A global shutter is a necessity in this field because objects move very fast...
To improve the electrical characteristics of LSIs, we are developing technology for embedding chip capacitors into interposers for LSIs. In this paper, we applied an interposer with embedded capacitors to an image-processing LSI and compared its electrical characteristics with that of a conventional LSI. We confirmed improvements in the timing margin, signal integrity, and immunity characteristics...
An 8.9-ENOB 40MS/s two-stage pipelined SAR ADC for a WLAN receiver is designed and fabricated in a 65 nm CMOS technology. The 1st stage is realized by a 1.5b/cycle SAR to mitigate the comparator offset issue. The 2nd stage employs a radix-1.8 SAR to avoid the parasitic capacitance issue. The presented architecture occupies 0.06 mm2 of area despite using a large unit capacitance of 60fF.
This paper illustrates different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topics to discuss and certainly impedance (Z)...
This paper proposes a local feedback, named auto correction feedback (ACFB), used in a chopper amplifier to suppress its offset related ripple. It nulls out amplifier's offset in DC domain which would otherwise become modulated ripple at the chopper amplifier's output, instead of filtering the ripple by a post filter. The proposed chopper amplifier with the ACFB achieves 45 dB ripple attenuation without...
This paper illustrates many different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topic to discuss in this paper and certainly...
This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18 um CMOS process, the 12-bits, 40 MS/sec ADC core consumes 7...
Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling capacitor (decap) allocation is one of the most effective way in reducing serious dynamic power noises (hotspots). To allocate decap before placement, we observed that not only locations but also rising time of functional cells...
A common-mode (CM) filter is usually used to remove CM currents on differential-mode (DM) signal lines [1]. However, in this paper we propose the application of an improved LC filter to reduce EMI noise of DM signal lines. The most important points of applying the LC filter are the consideration of the timing skew and notch points. It has been difficult to find the proper LC filter for DM signal lines,...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A novel compact coupled planar resonator (CCPR) based VCO (voltage controlled oscillator) using mode-coupling technique was developed in response to expensive high Ceramic and SAW resonators based signal source for wireless communications. One of the problems related to the conventional Ceramic/SAW based resonators (with high Q and low phase noise) is the challenge for integration in IC form. Instead...
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