The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The paper describes an approach for semi-symbolic analysis of mixed-signal systems that contain discontinuous functions, e.g. due to modeling comparators. For modeling and semi-symbolic simulation, we use extended Affine Arithmetic. Affine Arithmetic is currently limited to accurate analysis of linear functions and mild non-linear functions, but not yet discontinuities. In this paper we extend the...
The principle of full-bridge DC-DC converter is briefly expounded, including the two typical control methods, named limited dual polarity hard-switch control and phase-shifted soft-switch control. Then the common mode noise equivalent circuits of full-bridge DC-DC converter are deduced, taking the common mode noise of the bridge leg's midpoint into account, and the difference between the two typical...
This paper investigates the estimation of the coupled simultaneous switching noise (SSN) induced from power delivery networks (PDNs) in memory test boards. When the signal changes its reference plane in the board, voltage fluctuation occurs that induces the SSN in the PDN. This induced SSN affects other signals in the test board, reducing signal quality and test reliability. To avoid this problem,...
This paper illustrates different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topics to discuss and certainly impedance (Z)...
Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltage level, decaps can be used to improve the circuit performance as well. In this paper, we present the analytical delay model under IR drop, Ldi/dt noise, and decaps to study how decaps affect both the gate and interconnect delay...
This paper presents and verifies a co-modeling and investigation approach of noise isolation analysis in hierarchical power distribution network (PDN) for low-noise 3D system-in-package (SiP) design. It is based on a hierarchical modeling to combine the lumped circuit models at both on-chip level PDN and off-chip level PDN. The proposed hierarchical PDN model was successfully validated with good correlations...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper is concerned with the design and simulation of a pulse width modulation (PWM) rectifier for three-phase Permanent Magnetic motor drive. Based on the mathematical model of PWM rectifier, the dual-close-loop engineering design with decoupled feed-forward control is applied in the 3-phase voltage source rectifier. The objective to be reached is to realize unity power factor at the input ac...
A closed-form expression for via barrel-plate capacitances is derived. This results in a more accurate equivalent circuit model for decoupling capacitors including both parasitic inductances and via capacitances. Multilayer power distribution network (PDN) are then analyzed by incorporating the circuit models of both vias and parallel plane pair. Circuit simulator is used to evaluate the coupling...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
A primary source of common-mode (CM) electromagnetic interference (EMI) in high frequency switching converters is the parasitic capacitance between switching element and its heat sink. A passive method for cancellation of CM-EMI is analyzed in detail in this paper. Compared to with active cancellation techniques, it is much simpler and requires no additional switches or semiconductor components. The...
The use of the simulation program DIANA as a completely general design system for switched capacitor networks is presented, Using the example of a fifth order elliptical lowpass filter as a guide, time and direct frequency domain analysis, including all possible effects a.o. aliasing, resistive effects, opamp poles, etc..., as well as sensitivity and noise analysis are demonstrated. The program is...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.