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Consumer electronic products are evolving toward smaller size and higher efficiency. 3D IC packaging has smaller form factor and lower signal delay compared with conventional packaging. Thus, it has been widely used in mobile electronic devices. Mobile electronic device is prone to being dropped during operation. Hence, the drop reliability of electronic packaging is an important issue in 3D ICs....
ITRS has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials in flip chip technology will not be able to satisfy the thermal mechanical requirement these fine pitches. Of all the known interconnect technologies, nanostructure interconnects such as nanocrystalline Cu are the most promising technology to meet the...
This paper discusses the optimization of a stretchable electrical interconnection between integrated circuits in terms of stretchability and fatigue lifetime. The interconnection is based on Cu stripes embedded in a polyimide-enhanced (PI-enhanced) layer. Design-of-experiment (DOE) methods and finite-element modeling were used to obtain an optimal design and to define design guidelines, concerning...
Advantages of Cu wire bonding, such as less wire sweep, better performance for analog devices, are interpreted by its material properties. Alternative aspect from material properties on Cu wire bonding parameters is proposed to reflect the fact that Cu wire bonding may not necessarily damage the existing under-pad structure of integrated circuit designed for Au wire bonding. The challenge of Cu wire...
Sn-Ag-Cu (SAC) solders are susceptible to appreciable microstructural coarsening due to the combined effect of thermal and mechanical stimuli during service and storage. This results in evolution of joint properties over time, and thereby influences the long-term reliability of microelectronic packages. Accurate prediction of this aging behavior is therefore critical for joint reliability predictions...
Increasing demand, regarding to advanced 3D packages and high performance applications, accelerates the development of 3D silicon integrated circuit, with the aim to miniaturize and reduce cost. The study of the reliability of the through silicon via and of most critical areas for the emergence of failure remains a major concern. This paper deals with the variation of stress and strain induced in...
As far as components with flip chip interconnects are concerned, one of the popular packaging solutions available in the market is thermally enhanced flip chip ball grid array (TEFCBGA) packages, which target mid to high performance applications. Traditional as it may be, the development of a reliable TEFCBGA package is still a very challenging task. The demands for high electrical performance with...
Relative damage-index based on the leadfree interconnect transient strain history from digital image correlation, explicit finite-elements, cohesive-zone elements, and component's survivability envelope has been developed for life-prediction of two-leadfree electronic alloy systems. Life prediction of pristine and thermally-aged assemblies, have been investigated. Solder alloy system studied include...
In this paper, we demonstrate the application of digital image correlation (DIC) to the measurement of nanometer scale deformation in advanced packaging including flip chip and stacked integrated circuit dies. The application of DIC is shown to provide critical strain data which is useful for lifetime prediction of advanced packaging solutions. We show U and V deformation field contour (fringe) maps,...
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