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Owing to its multigate structure, the Multistate Electrostatically Formed Nanowire Transistor (MSET) enables the implementation of various fundamental analog and digital functions with fewer components compared, e.g., with CMOS technology. Due to its low off-current and overall low energy dissipation, the MSET can be regarded ideal for low-power IoT applications that operate at moderate frequencies...
The CCD is best suited to realize the wide band width systems with less expensive cost. Thus the CCD video delay line has been used to various consumer video signal processing equipment such as video cassette recorder In Improving picture quality.
Unquestionably, one of the most important developments in this century has been the avalanche advancement of Integrated Circuits technology incorporating solid state systems into areas never before imagined. Students face special challenges to understand these complex systems using conventional instructional methods. We here present a new pedagogical approach using the Variational Thermodynamic principle...
We propose a novel nLDMOS structure and a design concept in BCD technology with the best-in-class performance. The drift profile is optimized and the multi-oxide in the drift region is adopted to approach the RESURF limit of on-resistance vs. BVdss characteristic (i.e., 36V DMOS has a Ron_sp of 20mohm-mm2 with a BVdss of 50V; 45V DMOS has a Ron_sp of 28mohm-mm2 with a BVdss of 65V). Moreover, this...
We have developed 300 V Field-MOS FETs for High-Voltage switching IC. The breakdown voltages are 410 V/370 V with specific on-resistance of 1845/11000 mΩ·mm2 for Field-NMOS/PMOS FETs, respectively. The vertical and lateral electric fields are both optimized to maximize a breakdown voltage at wide range of substrate voltages and minimize a specific on-resistance with a device layout optimization by...
In this paper, we present a new isolated Low Vgs NLDMOS in 0.35um BCDMOS process. The proposed LDMOS is fully isolated from substrate and has very lower Rsp(specific on-resistance) than other competitors. This device can apply a negative bias to drain and it can be used in AMOLED application. The proposed LDMOS devices in 30–40V ranges have the lowest Rsp with other competitors in 0.13–0.35um BCDMOS...
In this paper, we report on the reduction of device resistance by up to 49% in junction isolated lateral double diffused metal-oxide-semiconductor (LDMOS) field effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on different state-of-the-art LDMOS field effect transistor concepts with and...
We report on using a single trench unit process for the trench isolation and for the trench power MOSFET of a common-drain smart power IC technology. The trench power MOSFET has a maximum specific on-resistance, (RonldrA), below 50 mOmega-mm2 and a typical breakdown voltage, Vbr, of 95 V. The trench isolation provides well isolation up to 90 V. Using a single trench unit process for both devices results...
A High-side Lateral Trench MOSFET (LTDMOS) was fabricated in a 0.35 mum ModularBCDtrade technology. The drift region of this device completely surrounds and isolates the trench, body, and source regions from the substrate, allowing the entire LTDMOS to float to a high-voltage above the substrate. A complete 28 V half-bridge level-shifter was demonstrated using integrated floating high-side drive circuitry...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
A planar edge termination technique of trenched field limiting ring is investigated by using 2-dimensional numerical analysis and simulation. The better voltage blocking capability and reliability can be obtained by trenching the field-limiting ring site which would be implanted. The trench etch step makes the junction depth deeper so that junction curvature effect and surface breakdown are less happened...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because it doesn't have a JFET region. But due to the electric field concentration in the corner of the gate edge, the breakdown voltage decreases.
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