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An adjustable pulse module with FPGA-based 0.1 ns resolution is designed, which has the function of simultaneously generating multi-channel pulse. Various pulses time delay can be adjusted each other. Therefore it can improve the small target RCS (radar cross section) test accuracy under the complex environment. At present, the technology is successfully applied to a RCS tester.
Time-Correlated Single Photon Counting (TCSPC) can provide not only the time information of a photon, but also the photon density information. Based on the conclusion of usual time interval measuring methods, this paper chooses the scheme of Time-to-Digital Converter (TDC) based on delay line structure, meeting the TCSPC system's requirement for high timing resolution. This TDC contains two delay...
This paper describes an eleven channel artificial nerve signal generator with a programmable inter-channel time delay using only a Field Programmable Gate Array (FPGA) and a small number of passive external components. The FPGA is used to create a novel, linearised Pulse Width Modulation scheme which would not be possible with other alternatives technologies such as a micro controller. This signal...
Various design-for-security (DFS) approaches have been proposed earlier for detection of hardware Trojans, which are malicious insertions in Integrated Circuits (ICs). In this paper, we highlight our major findings in terms of innovative Trojan design that can easily evade existing Trojan detection approaches based on functional testing or side-channel analysis. In particular, we illustrate design...
This paper presents a multi-channel Digital Programmable Delay Trigger System (DPDTS) with high accuracy and wide delay range, which can be widely used in laser system and electron accelerator. This DPDTS mainly makes up of reference clock module, user interface and control module and Digital Programmable Delay Trigger (DPDT) module which is implemented on a Xilinx V6LX75T FPGA. In this DPDTS, DDS...
A hardware-based solution of precise time synchronization over Ethernet was proposed for Networked Control System (NCS). Using Field-programmable Gate Array (FPGA), hardware-based solution was designed for implementing time synchronization protocol defined in IEEE 1588. Timestamp capture, oscillator frequency compensation, time synchronization and etc., were all coded with Very High Speed Integrated...
Devadas has first proposed the notion of Silicon Physical Unclonable Function (sPUF), which takes advantage of delay variations of wires and gates. A Ring-Oscillator-Based PUF (RO PUF) is one possible implementation of an sPUF. One disadvantage of RO PUFs is that they require one pair of ring oscillators per bit of output. Therefore, in order to collect enough output bits for a safe security level,...
Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power...
A novel spike-based computation architecture has been developed which represents synaptic weights in time. An analog chip with 32 neurons, 1024 synapses and an AER block has been fabricated in 0.5µm technology. A digital implementation of the architecture having 6,144 neurons and 100,352 synapses on an FPGA is also described. A digital controller for routing spikes can processes up to 34 million synapses...
This paper presents a 6 channels pulse width modulator with high resolution. The modulator is designed for three phase AC drives control. It is targeted for low cost FPGA implementation, and uses the special clock management units present in the FPGA. The modulator is verified first by measurements on one channel. Then it is used for open loop starting of a three phase induction motor, thus verifying...
To validate the effectiveness of a Physical Unclonable Function (PUF), it needs to be characterized over a large population of chips. Though simulation methods can provide approximate results, an on-chip experiment produces more accurate result. In this paper, we characterize a PUF based on ring oscillator (RO) using a significantly large population of 125 FPGAs. We analyze the experimental data using...
A design of the digital synchronous system which is based on FPGA is presented. To reduce the delay of the system logic and enhance the working frequency, the timing constraints have been analyzed. We investigate the influences of the delay of data output (Tco), the delay of combinational logic circuits (Tdelay), the setup time (Tsetup) and the clock cycle (T) on the working frequency, and adopt the...
The purpose of this paper is to present a new method and structure for the automatic configuration of a digital system to unknown delays in synchronous input data channels. The method makes possible to restore synchronism in node-to-node communication. Synchronism may be lost due to different delays introduced by the various communication channels. The proposed method allows differences in the channel...
In this paper a novel architecture for string matching is presented. It is oriented to an FPGA implementation and, differently from other similar works, it is particularly suitable for rules matching in multiple streams. The paper presents our developed architecture able to efficiently manage different streams, discusses how to optimize the design to limit the number of FPGA logic resources and shows...
Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on...
Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The major source of nondeterministic behaviors is clock domain crossing, because the clocks that determine the timing of events are sensitive to variations. In this paper, we propose a general...
Recent FPGA architectures facilitate the efficient mapping of high order compressors to implement multi-operand additions. This feature can be used to improve the performance and area utilization of large size multipliers. In this paper we present an improved design approach utilizing ternary adders and Generalized Parallel Compressors, GPCs, for the addition of the partial products. Multipliers of...
An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.
The construction and design process of a high-resolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been constructed, one based on the phase information delivered by the VIRTEX-5 Digital Clock Manager (DCM)...
The goal of this paper is to investigate the simulation capabilities of modern FPGA post-layout simulator (ISE from Xilinx) compared to real life behavior. A simple ring counter has been used as a test circuit and the delays between the outputs have been evaluated.
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