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In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks,...
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked...
A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller...
An analysis of high speed sample and hold circuit in different structure is presented. Performance and area comparison between two type of sample and hold circuit in low voltage is done. These different type of circuits are simulated and layout designed in 55nm CMOS technology. Both the structures based on a bootstrap switch that can acquire analog wave forms at sampling rate of 100MHz with 10 bit...
IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming...
An excessive switching activity during the functional capture cycles of scan-based tests can lead to overtesting of delay faults. Low-power test generation procedures that address this issue consider the switching activity of the fault-free circuit. This paper observes that an excessive switching activity in a faulty circuit can also affect the test application process. In particular, we show that...
This work presents the development of a four-channel correlated double sampling (CDS) ASIC, named CD-S4C, targeting the readout of a type of multi-readout swept charge device (SCD) for applications in the fields of both X-ray spectroscopy and imaging. Compared with conventional CDS architecture based on clamping technique, the innovation of the CDS4C ASIC is that it not only moves the clamping switch...
This paper proposes a bootstrapped sub-threshold leakage suppression switch for switched capacitor (SC) circuits that operate from a single supply voltage and acquire analog input that have zero common mode. The design is implemented using AMS 0.35 μm, 3.3 V CMOS process. The proposed switch gives best combination of linearity, leakage and swing. It improves the linearity of switched capacitor circuits,...
This paper reflects the study of a Power-Factor-Correction (PFC) boost converter's nonlinearity. A peak current controlled boost converter is simulated in continuous conduction mode (CCM) to study the dynamics through the bifurcation diagrams. The study shows that with changes of certain parameters the bifurcation and chaotic state may occur. The bifurcation diagrams indicate the stable zone of various...
A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
We have developed a high speed gate switching type Ku-band CMOS amplifier for direct RF undersampling receiver. This amplifier will synchronize its d.c. power switch timing to the sampling clock of the direct RF undersampling receiver. For Ku-band VSAT application, we designed the sampling clock frequency of undersampling receiver as 600 MHz, therefore the power switching time (Turn-On Time) of less...
A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated...
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
This paper presents a low-voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). An input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive-DAC (CDAC). By utilizing the comparator as a voltage-to-time converter (VTC) and implementation of time-domain quantizer, the input range is detected to...
In this paper, the design of sample and hold (S/H) circuit for 16 bit 100MS/s pipelined ADC is presented. A high performance and low power dissipation operational trans-conductance amplifier (OTA) is realized by optimizing circuit configuration and adopting switched-capacitor dynamic bias technology. A double gate-bootstrapping switch is used as the sample and hold switch to enhance the sampling linearity...
This paper presents a 10-bit 1 kS/s SAR ADC in 0.13μm CMOS technology for ECG signal recording applications. Two new techniques are introduced:1) a novel DAC switching method designed for fully-differential SAR ADC which reduces half size of capacitors and 50% DAC switching energy; and 2) a novel dynamic latch-type comparator bias circuit to eliminate static power consumption. Our simulation shows...
In recent years, there has been an ever-increasing interest in monolithic power supplies. Integrating the power supply with the application has many direct benefits, including a reduction of the bill of materials and reduced size. Even more substantial are the potential efficiency gains due to reduced power delivery network losses and voltage margins, especially in a world dominated by energy limited...
A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising...
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