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This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks,...
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked...
Integration of digital RF transmitters and digital power amplifiers (DPA) is becoming of great interest for systems-on-chip (SoCs) available in nanometer technologies [1]. Small and high-speed switching devices directly benefit switching power amplifiers in achieving peak power with high peak efficiency. However PA back-off efficiency remains a big challenge in high-data-rate systems with large peak-to-average...
An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR...
Wide bandgap semiconductors allow for the potential of expanded temperature ranges for power and mixed-signal applications. Developments in a Silicon Carbide (SiC) CMOS integrated circuit process have demonstrated high temperature operation at 400 °C and above, paving the way for a SiC-controlled SiC power electronics system capable of operating at high temperatures. A two-phase clock generator with...
In this paper we present a 10-phases programmable clock generator for the application in control of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC), realized in the CMOS 130 nm technology. The circuit provides 10 clock signals on separate terminals (sections). The programmable feature means that we can program the number of clock phases which are cyclically repeated. The...
A compact, extensible lab network is described that is suitable for implementing multi-protocol label switching (MPLS) and other network protocols for research and instructional purposes. Service provider and customer requirements can be modeled. Freely-available tools were used to test network congestion performance and important limitations to their capabilities were observed. Results also showed...
Early design space exploration has been shown to be an important factor in reducing the development time for Network on Chips. In this paper, we present a Matlab toolbox aimed at the early-stage design space exploration for NoC router design, the router founding element of a NoC. The toolbox is based on the discrete event simulation engine SimEvents. The presented toolbox can be used to graphically...
This paper describes the design, implementation and analysis of FPGA based High Frequency Switching Sinusoidal Pulse Width Modulation (SPWM) generator for the application of three-phase DC/AC inverters using Pipelined CORDIC algorithm. The carrier frequency of up to 4 MHz and operating frequency of 256 MHz is achieved. The switching frequency can be dynamically reconfigurable on real time by the user/external...
Nanosatellite has limited functions because of the mass constraint from 1 to 10 kg. Therefore, the requirement of low cost, low mass, low dimension, and low power consumption must be fulfilled in designing and choosing the component of nanosatellite. To obtain wider coverage area while maintaining the low dimension, camera array was used to produce image with wider area. In this research, On Board...
We introduce a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that delivers near-threshold (NT) output voltages. The converter is built in 28 nm UTBB FD-SOI and occupies 0.0104 mm2. Back-gate biasing is utilized to increase the load power range. Measurements show a peak efficiency of 87%, self start-up capability, and a minimum efficiency of 75% for 79 nW to 200 μW...
A high-resolution second-order integrating sigma-delta analog-to-digital converter (ADC) using double-sampled integrators is presented whitch performs two times faster sampling than conventional modulator. The modulator has been designed in a 0.18-um CMOS technology. It acheives a signal-to-noise and distortion ratio (SNDR) of 93.03 dB at a conversion rate of 64 sample/s. Power dissipation is 36µW...
A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current at negative temperatures, the need for an extra digital supply IO, and the clocking power costs faced by the internet-of-things (IoT) and wearable systems. The system includes:...
Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the...
In this paper, a digital background calibration scheme using an 8-b 10-MS/s successive approximation register (SAR) ADC to calibrate an 8-b 100-MS/s pipelined folding ADC is presented. In order to sample high frequency differential input signals, a new SAR ADC architecture based on the monotonic switching procedure is also proposed. Both ADCs are designed using a 0.18 µm CMOS technology. From the...
This paper presents a low power True Random Number Generator (TRNG), based on the discrete time-chaos, intended for a RFID security applications, to be developped on CMOS 350nm standard technology. The circuit relies on a discrete time chaotic oscillator to generate patterns to be sampled to get a raw random signal to be debiased by a digital corrector.
This paper proposes a new concept of adaptive ramp generation to enhanced the transient response of PWM voltage mode buck converter. Based on a simple ramp slope controller, the proposed adaptive ramp generator can output ramp with different slopes to accelerate duty ratio adjustment so as to reduce the voltage variations (voltage spikes) and the transient recovery time. A PWM voltage mode buck converter...
A 12-bit counter ramp recycling analog-to-digital converter (ADC) is proposed, which can be configured in a single-step mode for achieving high conversion accuracy as well as in various multi-step modes for yielding high conversion speed. A unique ADC circuit realization is used for the different modes of operation, while a digital control unit is responsible for providing the necessary control signals...
This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented...
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