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As gains in integrated circuit power and performance achieved through scaling of feature sizes slows, system and circuit design must carry more of the burden for improvement. Aggressive design decreases guardbands, increasing the risk of circuit failure. This paper discusses the increasing need for embedded on-chip sensors to enable aggressive design and also to help counter the attendant increased...
The latest trend towards performance asymmetry among cores on a single chip of a multicore processor is posing new challenges. For effective utilization of these performance-asymmetric multicore processors, code sections of a program must be assigned to cores such that the resource needs of code sections closely matches resource availability at the assigned core. Determining this assignment manually...
This paper propose a scheme of CAN-Bus universal interface module base on USB, The scheme uses USB chip CH375, CAN chip SJA1000, and uses MSP430F449 as control unit to complete USB, CAN interface control, as well as between the data processing and others. This paper also introduces software process and PC application program. In order to record the transmission time interval of the CAN information...
We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs). Compared to CPU-based commodity systems, our solution shows distinctive advantages for stream monitoring tasks, e.g., wire-speed processing and predictable performance. The demonstration is based on a query-to-hardware compiler for complex event patterns that we presented...
The paper presents design and implementation of a wireless sensor node suitable for medical applications. As physiological signals are highly redundant, the data compression algorithms (Huffman's coding) are used to save energy and improve the node performance. Design is based on the ARM Cortex M1 processor and implemented in FPGA.
We proposed power line communication (PLC) through a microprocessor's power distribution network as a novel technique for communicating to any node inside a chip and demonstrated the suitability of Impulse Ultra-Wideband (UWB) communication. Applications of this scheme discussed in this paper exemplify the applicability of this scheme in future microprocessors. Further, data recovery block design...
Integrated circuit aging effects are more and more pronounced with the continuous technological downscaling. These effects degrade circuit operation which is mainly observed as increased input-to-output delay of circuit components. Eventually, the circuit falls out of its specifications. Countermeasures are needed to prevent or reduce such degradation. Aging monitoring can be very beneficial since...
This paper presents an on-line distributed induction motor monitoring system based-on the ARM (Advanced RISC Machines), which is integrated with the embedded and CAN (Controller Area Network) bus technologies. The hardware structure of the system with the ARM microprocessor S3C2410X and CAN bus controller MCP2510 is introduced, the accomplishment of software of motor on-line monitoring system is also...
Neuromorphic systems have been increasing in size and complexity in recent years, thanks also the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. AER mapper devices that route Address-Events from multiple sources to different multiple destinations are crucial components of these systems, as they allow...
Current generations of high performance microprocessors feature multiple cores and micro-cores, with each supporting multiple threads implemented in hardware. Such designs routinely feature billions of transistors, and chip layout teams are frequently hard pressed for placement and routing of all the functional blocks and sub-blocks that go into the design. An additional complexity arises because...
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilization is becoming ever more important. Furthermore, available cores are expected to be underutilized due to the power wall and highly heterogeneous future workloads. This trend makes existing L2 cache management techniques less...
The next generation in the Intel® Itanium® processor family, code named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium® Processor 9300 series (Tukwila) . The new design integrates a ring-based system interface derived from portions of previ ous Xeon® and Itanium® processors, and includes 32MB of Last Level Cache (LLC). The processor is...
The growing popularity of mobile internet services, characterized by heavy network transmission, intensive computation and an always-on display, poses a great challenge to the battery lifetime of mobile devices. To manage the power consumption in an efficient way, it is essential to understand how the power is consumed at the system level and to be able to estimate the power consumption during runtime...
The characteristic of dramatic fluctuation in the resource provisioning for real-time applications calls for an elastic delivery of computing services. Current data center deployment schemes, which feature a strong tie between servers and applications, are increasingly challenged to ensure power efficiency in terms of multiple peak loads provisioning, optimal average resources utilization, variable...
In order to solve the real-time monitor problem and large-scale network monitor problem in wireless network communication of power grid environment monitoring system, a power grid environment monitoring system based on WLAN is designed. The ARM+Linux embedded operating system and WLAN are used at the system monitoring terminal to gather, process and convey the power grid environment monitoring data...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key observations, based on our study of LLCs: 1) the capacity demand is highly non-uniform and dynamic at the set level, and 2) neither spatial nor temporal LLC management schemes, working separately as in prior work, can consistently...
The dust concentration and particle size are real-time monitored at the electrostatic precipitator (ESP) entrance and exit by laser measurement with bypass dilution device. The accuracy of the monitor data is improved by the method of collecting and transferring eight sites signal simultaneously. And the data is transferred by RS485 bus and related agreement. The ESP voltage in electric field is real-time...
Supervisory Circuits are designed for various type of application. It comes as discrete devices as well as On-Chip solutions and is indispensable to initialize some critical nodes of Analog and Digital designs during Power failure. In this paper, we present an Integrated Microprocessor Supervisory Chip specifically designed for Microprocessor peripheral devices. The new design chip provides three...
This paper proposes a security paradigm named self-existent mechanism of access control. The most distinct character is that it runs absolutely independent from program executing environment, even without cooperation of OS. That is to say, it has a unique structure to assure that computing is controlled under a secure mechanism that cannot be penetrated by software like virus, Trojan and other malicious...
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