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In recent years there has been a growing interest in Internet of Thing, Big Data and Mobile Internet. With the rapid growth of the amount of data in the embedded environment, using a traditional embedded processor is hard to satisfy the requirements of big data processing. Sorting is one of the fundamental operation in data processing and is also frequently used for search, filter, feature analysis...
Cellular Automata with Random Memory (CARM), which has been recently introduced, is a time-delay discrete time system such that delay is a random variable. Delay in discrete time systems can be easily generated from a random delay characteristics of wires and transistors in programmable logic devices. Therefore implementation of CARM model is not required any special hardware. In this paper, a new...
In this paper, we aim at increasing the strength of weak arbiter physical unclonable function (APUF) which are vulnerable to modeling attacks because of low uniqueness and randomness. We propose a unique technique which takes n × 1 challenge-response pairs (CRPs) from APUF and combines them with ring oscillators (ROs) implemented on the same FPGA to get n × n CRPs. We claim the proposed technique...
When learning different control related concepts and methods, simulation is often used as a training tool; but, it does not have some real time characteristics of implementation like dealing with coding and PC resources, supervision, and communications. In some cases, implementation cannot be carried away, since it involves hardware design and is expensive. The proposed solution in this paper involves...
In this paper, we propose a high accuracy multi-chain time interval measurement (TIM) technique by employing the dedicated carry chain of FPGA. According to the principle of delay chain time to digital converter (TDC), the proposed method is realized by connecting the selectors inside the slices. The resolution of the delay chain method is limited by the time delay of one delay unit. To break through...
Parallel FIR filter is widely used among various types of filter in Digital Signal Processing (DSP). This paper shows the design of area-efficient 2-parallel FIR filter using VHDL and its implementation on FPGA using image system. This paper gives the details basic blocks of area-efficient 2-parallel FIR digital filter. In this paper proposed 2-parallel digital FIR filter and area-efficient 2-parallel...
A standard priority-queuing system is capable of arranging packets with different traffic classes to guarantee a relatively low latency for the high priority traffic. However, in practical cases, severe delay may be caused by starting a large, low-priority frame ahead of a time-critical frame. In this paper, interspersed express traffic is evaluated, which enables preemption of non-time-critical transmission,...
In this work, a high throughput architecture for 1-D Discrete Wavelet Transform is proposed. The work proposes DWT computation through convolution of a ‘M’ point input sequence with a ‘L’ tap wavelet coefficients. Computation of DWT of an N point sequence is carried out by summing the results of blocks of ‘M’ points. For illustration, an 8 tap filter and block size of 4 is considered. Through poly-phase...
Many n-D signal processing applications in industrial environments require real-time processing of data. We propose a technique for realization of motion feature extraction in video images on low performance computing hardware. The realization is based on a 2-D spatio-temporal wave digital filter (WDF) using SDRAM-based shift operators. This enables the usage of different effective shared bus widths...
A method of retiming the spatial synchronous dataflow graph (SDF) is proposed, which is based on the SDF representation in the multidimensional space. The dimensions of this space are the spatial coordinate of the processing unit, coordinate of the operator firing and operator type. At the first stage of the datapath synthesis, the operator nodes are placed in the space according to a set of rules...
As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new...
Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption...
This paper presents the design and implementation of a 64-bit VLIW microprocessor. It discusses the concept, traits, principle and structure of this 64-bit VLIW microprocessor to facilitate its design. This paper first discusses the architectural specifications of the microprocessor and the 16 kinds of operational functions it facilitates. It then examines the implementation of the whole VLIW microprocessor...
This paper presents new system-level design for the cognitive sensor based on energy detection to boast the performance accuracy by maintaining a queue of energy samples and computing their average to determine the decision threshold. Thereafter, these values summed over average number of samples are again compared with the recent energy value to decide whether the spectrum is occupied or unoccupied...
Polar codes, introduced by Arikan, achieves the capacity of symmetric channels with “low encoding and decoding complexity” for a large class of underlying channels. Recently, polar code has become the most favourable error correcting code in the viewpoint of information theory due to its property of channel achieving capacity. Although the fully parallel polar code based encoder architecture processes...
A high performance substitution box (S-Box) FPGA implementation using Galois Field GF (28) is presented in this paper. An optimum number of pipeline registers based on Spartan-3E FPGA is addressed in this paper. The design is fully synthesizable using Verilog and can easily be converted to ASIC implementation. As a result, a fast and area efficient implementation of pipelined S-Box was synthesized...
The aim of this paper is to design multiplier circuits for artificial neural network applications. The efficient use of area and speed performance has become a challenging task VLSI design field. In this works, radix-4 booth multiplier and radix-2 booth multiplier algorithms are analyzed based on its area used and speed performance. The less area used means the multiplier is more efficient in usage...
Complex numbers multiplication is a key arithmetic operation to be performed with high speed and less consumption of power in high performance systems such as wireless communications. Hence, in this paper, two possible architectures are proposed for a Vedic real multiplier based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra of Indian Vedic mathematics and an expression for path delay...
In order to enhance the characteristics of underwater ultrasonic imaging system with small volume, low power supply voltage and easy integration, the underwater ultrasonic phased transmitting system is designed. Using field programmable gate array (FPGA) to control the excitation signals time-delay of 16 channels to achieve phased transmitting, and capacitive micro-machined ultrasonic transducer arrays...
The authors present an implementation technique of a novel system which can be used to perform 3-D filtering for separable kernels. The structure, consisting of Givens rotations and delay elements, is implemented in FPGA chip. Givens rotations are based on a pipeline CORDIC algorithm. Presented approach is tested against finite precision noise and sensitivity to structure parameters. It is shown that...
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