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In this paper single operational transresistance amplifier based lossless grounded negative inductance simulator topology is presented. The proposed circuit employs only single OTRA and four passive elements. The circuit is studied for nonideality and high frequency self compensation is achieved. Theoretical propositions are verified by simulation.
High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternates data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode...
The two-stage amplifier design has been well studied in past decades. Many high performance amplifiers have also been proposed by various researchers. However, it is hard to find a standard design flow for an amplifier. Hence, in this paper, we propose a standard flow to design a two-stage amplifier. By applying the standard design flow, an analog circuit designer can speed up the whole design procedure...
In this work, the design of a 94GHz rotary traveling wave oscillator (RTWO) is presented. The oscillator targets mm-Wave transceivers for biomedical imaging applications. A design procedure to minimize the total power consumption is presented. Using this proposed procedure, a 4 section RTWO is designed in a 65nm CMOS technology. The oscillator consumes 80mA (including buffers) from a 1V supply, and...
This paper presents an alternative linear topology for conditioning resistive sensors. This topology allows us to obtain an inherently linear relationship between the variable measured by the sensor and its corresponding output, which is not always valid for the topologies most commonly employed in industrial applications, such as the Wheatstone bridge. SPICE simulations of this alternative topology...
A three stage single-ended LNA using transformer (TF) matching and gain-boosting by capacitive feedback for wideband operation in the 57–66GHz band is presented. The LNA, fabricated in a 65nm standard CMOS process, achieves a 23dB-gain 4dB NF at 6mA and 1.25V supply, with 2dBm Psat and 0.05mm2 in size, demonstrating best reported noise figure, gain, power consumption and chip area compared to published...
Analysis of several impedance matching networks used in both common source and common gate amplifiers with reactive feedback are presented. Five fundamental topologies for transformer feedback based closed-loop amplifiers are identified and their relative merits with respect to silicon area and power consumption are discussed. In addition, a design methodology to achieve both narrow and wideband matching...
For an analysis of large networks including nonlinear active devices and coupled elements, conventional SPICE-like simulators suffer from a large amount of computational cost due to time-consuming direct matrix operations. In order to overcome the problem, the block-latency insertion method (block-LIM) has been proposed as a fast circuit simulation technique. The advantage of the block-LIM is employing...
In this paper a novel CMOS latch is designed using a class-AB transconductor as a core. The static latch behavior is studied using a homotopy method which allows highlighting sufficient conditions for the transconductor to become a latch. These last conditions are general and can be used for the design of new latches and comparators. The proposed latch features high speed together with high power...
Successive approximation analog-to-digital converters are very attractive to power-constrained applications due to the topology inherent energy efficiency. This converter architecture most often relies on digital controller circuit to guide the conversion algorithm, and this controller is reported to have an important impact on the overall power consumption, sometimes demanding roughly half the total...
In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After...
This paper presents a CMOS latched comparator designed for low power analog to digital conversion application. The circuit consists of a rail-to-rail operational transconductance amplifier followed by a dynamic latch to achieve a fast, high resolution performance at low power. The regenerative latch efficiently reduces the number of gain stage needed and consumes negligibly small static power. The...
Asynchronous circuits are well known for their intrinsic robustness to process, voltage and temperature variations. Nevertheless, in some extreme cases, it appears that their robustness is not sufficient to guarantee a correct circuit behavior. This limitation, which is caused by an analog phenomenon, appears when the transition slopes in input of C-elements become very slow. This paper describes...
Analysis concentrated on noise performance issues of a CMOS high gain second generation current conveyor (CCII∞) is presented using both simulations and measurements results. The circuit has been fabricated in a 0.35 μm CMOS process by Austria Mikro Systeme (AMS) and it is examined analytically in terms of the noise contribution of each transistor in an inverting voltage amplifier configuration. Preliminary...
A 23 dBm class E power amplifier (PA) has been designed and simulated at 3.7 GHZ using a 130 nm CMOS-SOI technology. The PA is a single stage, single ended cascode formed by a thin oxide transistor as common source device and a laterally diffused MOS (LDMOS) transistor as common gate. Fully integrated high current inductor is used as part of the class E wave shaping network. At 3.7 GHz, the PA achieves...
A comprehensive analysis of the impact of geometric parameters on the design of millimeter-wave integrated transformers is presented. Transformers presenting the same stacked topology but different diameters and trace widths were fabricated in a 65 nm CMOS technology and their performance was compared in terms of inductance, quality-factors, coupling coefficient and minimum insertion loss. Results...
In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation...
This paper presents an alternative topology for realizing a four-quadrant amplifier with single-ended output. In the proposed multiplier, constituting differential circuits are vertically arranged resulting in single-ended current output with output DC voltage equal to a half of supply voltage. Since the circuit operates in a current-reused mode, the power consumption is systematically reduced by...
In this paper, we present the low noise amplifier using new feedback connection configurations. The UWB LNA is design in 0.18 mum TSMC CMOS technique to achieve high gain, small size and low noise. The LNA achieved 11 dB of average power gain, low 2.87 dB noise figure (NF), -10.9 dB input match, -7 dB return loss, -3 dBm of IIP3 and only 0.54 mm2 size with 15 mW power consumption.
In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and...
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