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This paper describes a resistorless current reference source, e.g. for fast communication interfaces. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology....
In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. The created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge...
A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The...
In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. The NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor...
In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and...
In this paper, a built-in current (BIC) monitor for testing low-voltage digital CMOS circuits is presented. The monitor is designated for typical IDDQ testing as well as for characterization of supply current values for different test vectors. Voltage drop across the monitor during measurement and the switching phase are minimized. A wide range of currents is supported. Abilities and limitations of...
A new compact low power voltage reference source for wireless and embedded applications is described. The reference voltage source has been designed in a mixed-signal UMC 90 nm CMOS process using subthreshold characteristics for generating a constant voltage of 423 mV at supply voltages from 1.1 V to 3.3 V with total current consumption 270 nA. The proposed circuit occupies 0.001 mm2 chip area and...
This paper describes a unique remote laboratory for studying CMOS physical defects that is meant to be used in advanced courses in the scope of microelectronic design and test. Both the measurement equipment and the remote access mechanism were custom developed in the frame of the European Union project REASON. The core of the equipment is an educational chip that contains different manufacturing...
W artykule przedstawiono metodę generacji testów wykrywających uszkodzenia układów cyfrowych CMOS spowodowane zwarciami ścieżek. Zadanie to wymaga analizy topografii układu przy znajomości statystyki wielkości defektów powodujących zwarcia. W rezultacie każdemu wektorowi wejściowemu zostaje przypisane prawdopodobieństwo wykrycia przez niego uszkodzenia układu. Zaprezentowano efekty charakteryzacji...
This article describes a measurement environment for study of two CMOS defect types: opens and shorts. These defect types are physically implemented in silicon in a big variety of locations inside a set of digital standard cells and small circuits. The integrated circuit (IC) with the collection of defects is mounted onto a plug-and-play measurement box, which is connected to the PC via USB cable...
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