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This paper presents a voltage-mode loser/winner-take-all circuit that has high speed and accuracy with low power consumption and which is suitable for LED driver applications. The implementation mixes analog and digital circuits in order to help in improving precision. The design is based on a hysteretic comparator and, as such, achieves a very fast response time. The circuit is implemented in the...
Most of the advanced CCD sensors require bipolar clocks with large voltage swings. Hence there is a need of voltage level shifter to translate TTL/CMOS compatible levels to bipolar voltage swings (up to 20V). The CMOS drivers have advantages of low power and high input impedance but its main challenge is to attain negative voltage swing. Hence different topologies have been studied to implement the...
In this paper, the effect of N-well for single event upset in 65nm CMOS triple well technology SRAM CELLS is studied. The study shows that charge sharing collection increases because of the existing of N-well in triple-well technology. While it restrains the single event upset and reduces the soft error rate (SER) compared with the SRAM whose NMOS are dual-well technology devices. The result of this...
This paper presents an accurate analytical delay model for CMOS inverter considering both subthreshold and superthreshold operating regions. Previous related work are either only valid for a specific operating condition or assume a step input. Therefore, that is the first approach to consider both different operating regions and input transition time. Moreover, the proposed model also considers several...
In this paper, the effect of N-well for single event upset in 65nm CMOS triple well technology SRAM CELLS is studied. The study shows that charge sharing collection increases because of the existing of N-well in triple-well technology. While it restrains the single event upset and reduces the soft error rate (SER) compared with the SRAM whose NMOS are dual-well technology devices. The result of this...
We have designed the full Adder using hybrid-CMOS logic style by dividing it in three modules so that it can be optimized at various levels. First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a good driving capability. It also consumes minimum power and provides better delay performance. Second module is a sum circuit which is also a XOR circuit...
In our previous studies [1], [2], good power supply wirings on a chip have provided excellent high-speed switching and tinny power swing fluctuation. In this study, we again confirmed this by higher precision re-measurements correlated with simulations. If the power integrity (PI) would be better on the circuit, the circuit would be expected that the CMOS driver makes it sure to take higher-speed...
The reduction in the operating voltage play a majorrole in improving the performance of the integratedcircuits.Apart from that lesser power consumption, reducedarea and smaller size of transistors are also the vital factors inthe design criteria and fabrication of the systems. This articleapproaches towards the increasing performance of the systemsby comparing different types of adder circuits. In...
The paper presents an equivalent circuit of LNA with different ESD protection structures, which are used to discharge the excess power. The two different circuits are physically implemented and extracted in 0.18µm CMOS technology. The goal is to realize LNA with ESD protection and to run post extract simulations, to see how parasitic elements influences of the LNA's work under certain conditions....
This paper presents a compact bidirectional current mirror suitable for low voltage applications. The idea is to use complementary transistors in subthreshold which are able to set a reduced bias current through the mirror. The circuit presents a class AB operation with a THD near to 1% at 1MHz. The bandwidth is above 10MHz as shown by simulations using Spectre with 0.5μm CMOS technology parameters.
This paper describes a fast transient simulation technique based on a block-type leapfrog scheme for general nonlinear circuits. In existing leapfrog-based techniques, there is a restriction on dealing with nonlinear elements in the circuit. On the other hand, the block-type leapfrog scheme is suitable for the simulation of tightly coupled networks such as the equivalent circuit of multiconductor...
This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range....
The scaling of key analog properties of CMOS technology under low-voltage conditions, in weak and moderate inversion, is investigated with emphasis on temperature behavior. Design parameters, such as weak inversion slope factor, threshold voltage, mobility, transconductance to current ratio, DIBL, and intrinsic gain, are examined with respect to bias conditions, geometry and temperature. Guidelines...
The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current....
A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by mixed-mode simulation and experimentally validated. The new clamp is composed from stacked NMOS driver and power BJT to achieve appropriate voltage tolerance. Both NPN and PNP-based versions of the clamp are compared to the stacked NMOS clamp.
In this paper, a novel built-in sensor (BIS) for digital CMOS circuit testing has been proposed. The proposed BIS has no voltage degradation and it is able to detect, identify and localize both open and short circuit faults. Moreover, it has a simple realization with very small area and detection time. A 4×4 multiplier cell is tested by the proposed BIS and all injected faults are detected.
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
In this paper, we propose new circuits for the implementation of Radial Basis Functions (RBF). These RBFs are obtained by the subtraction of two differential pair output currents in a folded cascode configuration. We also propose a multidimensional version based on the unidimensional circuits. SPICE simulation and experimental results indicate good functionality. These circuits are intended to be...
An accurate min-max current selector is designed and simulated. Given two input currents, it sorts them so that a copy of the smaller of the two input currents appears at one output, and a copy of the larger input current appears at the other output. The min-max current selector operates for input currents ranging from 70 μA to 90 μA, that is, over a range of 20 μA. It has been designed and simulated...
This paper deals with the design of an LC Voltage Controlled Oscillators using MHS SCMOS3 0.5 μm process. A sizing method is proposed to meet the WiFi and Bluetooth standards requirement. The layout of the circuit with CADENCE environment has been accomplished. Based on this layout, post layout simulations were performed and circuit improvement has been proposed in order to overcome parasites drawback.
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