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In this paper, a 14-bit low power self-timed differential SAR ADC with a new structure high precision multi-segment bandgap reference (BGR) is presented. In this design, Self-timed bit-cycling is adopted to enhance the time efficiency. Gray coding form mode control words are utilized instead of binary for mode control to reduce substrate noise and enhance the linearity of the whole system.
The design plan and HSPICE measurement of a high acquisition speed for a sample of 8-bit CMOS differential successive approximation register (SAR) Analog-to-digital converter (ADC) are presented. The operation of the conventional main switch-capacitor array is divided into two switch-capacitor arrays. Such that, one switched-capacitor array is used to define the four most-significant bits, while the...
CMOS active pixel sensor (APS) is currently the most popular image sensor architecture. In this paper, a CMOS active pixel image sensor with analog-to-digital converter (ADC) is presented. The driving controller of the image sensor is implemented on CPLD chip in the real-time mode, and performed successfully. The detailed design of the image sensor driving circuit is provided. Some codes with VHDL...
An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves...
This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power...
In order to reduce the design difficulties, the input sample-and-hold amplifier (SHA) is often removed in the nested background calibration of the CMOS pipelined analog-to-digital converters (ADC). The system uses a dual-channel LMS adaptive digital background calibration algorithm, and the reference ADC was calibrated in the foreground. Without the input SHA, the sampling-time error between the two...
This paper proposes a Volterra-enhanced model to evaluate the impact of substrate noise on CMOS regenerative comparators and on flash A/D converters. The presented approach initially extends the linear model of the non-uniform sampling (NUS) distortion of the comparator due to substrate noise, to include 2nd and 3rd order non-linearities. The effectiveness of the enhanced model is then evaluated by...
A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81...
Analog-to-Digital (A/D) conversion is faced with strong requirements in terms of resolution and frequency. Time-Interleaved Analog-to-Digital Converters (TIADC) are popular because they offer a higher sampling frequency. But, their architecture introduces errors that affect the resolution of conversion. This paper presents a built-in method of calibration dedicated to TIADC. Mixed-simulations are...
A 12-b 40-MSamples/s low power CMOS pipelined analog-to-digital converter is described. A novel switched-capacitor multiply-by-two amplifier with an accurate gain of two is proposed for pipelined ADC. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power...
A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power hungry sample-and-hold amplifier can be removed and rail-to-rail input can be used. In addition, feedback factor of the first MDAC can be increased, which...
A capacitive charge-sharing, decision feedback equalization (DFE) circuit is presented for use in high-speed serial link receivers. Similar to the capacitive DAC (digital-analog converters) used in successive approximation-based ADCs (analog-digital converters), the proposed one-tap DFE with half-rate quantizer demultipliexing operates at 4Gbps, consuming 0.32 mW from a 1-V supply, excluding clock...
A novel design and measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52??W at a bitclock of 50-kHz and of 0.85??W at 100-kHz with a 1.2-V supply. The Figure-of-Merit reached with such implementation is...
A 6b 65nm CMOS ADC exceeds the 29GS/S requirement of a 58Gb/s DP-QPSK optical receiver while operating up to 40GS/S. An inter-leaved architecture combines 16 SAR converters and an array of T/Hs with delay, gain, and offset calibration. A 1V 40mW 2.5GS/S subADC results in a total power of 1.5W, ENOB of 4.5b (3.9b) up to 10GHz (18GHz). An on-chip signal synthesizer simplifies production testing.
An 8.9-ENOB 40MS/s two-stage pipelined SAR ADC for a WLAN receiver is designed and fabricated in a 65 nm CMOS technology. The 1st stage is realized by a 1.5b/cycle SAR to mitigate the comparator offset issue. The 2nd stage employs a radix-1.8 SAR to avoid the parasitic capacitance issue. The presented architecture occupies 0.06 mm2 of area despite using a large unit capacitance of 60fF.
A Hybrid CLS-opamp/ZCBC pipelined ADC is introduced to improve accuracy, robustness, and power efficiency. Fast and accurate residue amplification is achieved by invoking a short ZCBC operation followed by CLS-opamp settling. Measured ENOB is better than 11 b at sampling rate of 20 MHz.
Applications like ultra-wideband radio, optical communication require sampling rates of at least 500 MS/s with low resolution. The potential energy savings of successive approximation based time-interleaved A-D conversion architecture overrides traditional flash architecture. This paper presents a 6-bit 800 MS/s ADC in 65 nm STMicroelectronics standard CMOS process. The ADC uses 8-channel time interleaved...
This paper reports on a modified architecture for single-slope integrating analog-to-digital converter (ADC) for use in image sensors and biomedical or any other applications where the value of the input analog signal has small and slow variations. In this architecture, instead of digitizing every new analog sample independently, the difference of the new sample with the previous sample is digitized...
An undersampling 14-bit 357 kSps cyclic ADC is designed for radio frequency identification (RFID) transceiver system. Modified passive capacitor error-average (PCEA) technique is adopted for high accuracy. Opamp sharing and the removal of front-end SHA are utilized for low power dissipation and small chip area. The proposed chip is fabricated in a 180 nm CMOS process, and it occupies 0.65 mm ?? 1...
This work presents a novel flash analog-to-digital converter (ADC) with low input capacitance. Utilizing the proposed distributed track-and-hold pre-comparators (THPCs) architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18 mum CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate...
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