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This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero...
This paper describes a single pole, double throw (SPDT) CMOS SOI switch in 180nm Technology developed for the GSM 900MHz RF switch applications. Silicon-on-Insulator (SOI) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulator substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOI FET has a very low Ron-Coff...
Applications like ultra-wideband radio, optical communication require sampling rates of at least 500 MS/s with low resolution. The potential energy savings of successive approximation based time-interleaved A-D conversion architecture overrides traditional flash architecture. This paper presents a 6-bit 800 MS/s ADC in 65 nm STMicroelectronics standard CMOS process. The ADC uses 8-channel time interleaved...
A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit and a pull up protection circuit. When a high voltage is applied to the...
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