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A wideband tunable divide-by-4 is designed and realized in 28nm bulk CMOS. A systematic design methodology to maximize the locking range over power consumption ratio is proposed. The test chip core area is only 25.6×24.8μm2 and measurements repeated over several samples demonstrate an operating frequency range from 25GHz to 102GHz with a maximum power consumption of 5.64mW from a 0.9V supply. The...
A 1.2V wide-band programmable divide-by-N frequency divider (FD) with consecutive 16-519 division ratios has been designed and fabricated using standard 90nm CMOS technology. The programmable FD consists of a high speed divide-by-8/9 dual-modulus prescaler, a pulse counter (P counter) and a swallow counter (S counter). Dynamic current-mode logic (DCML) DFF and signal locking technique have been used...
In this paper, a K-band frequency synthesizer using 0.18-µm CMOS technology is presented. To achieve low-power consumption, a transformer-feedback voltage-controlled oscillator (TF-VCO) with a cascoded current mode logic (CML) frequency divider is proposed. Furthermore, the push-push structure is selected in TF-VCO to overcome the design trade-off between operating frequency and dc power consumption...
This paper presents a low-power true single-phase clock 2/3 prescalers at 1.2 V supply voltage. The true single-phase clock divider was developed to help achieve low power and highspeed. All simulation results have been carried out by using Hspice program simulator based on 0.13μm CMOS technology. The power consumption of the proposed circuit is less than that of the previous circuits. The prescaler...
This paper presents a non-Boolean digital logic technique used in the design of a high-speed and low-power frequency prescaler. Maximum achievable frequency input of prescalers is limited by the number of devices connected in cascade to the high-speed signal path. In this work, a reduced number of devices is obtained in the prescaler by realizing implication logic operators with a single-phase digital-based...
This paper presents a novel high performance readout integrated circuit (ROIC) for conditioning and acquiring raw sensor signals for a frequency based converter platform. It consists of specific circuitry designed to interface capacitive sensors with high efficient frequency-to-code converters powered by an ultra-low temperature dependent voltage reference circuit. Thanks to a controlled compensation...
A frequency-tracking technique together with a single-coil distributed differential inductor is proposed to enhance the locking range of mm-Wave injection-locked frequency dividers (ILFDs). Implemented in a 65nm CMOS process, the proposed ILFD measures a locking range of 39.2% from 53.4GHz to 79.4GHz and consumes 2.9mW from a 0.8V supply corresponding to FOM of 8.97 GHz/mW while occupying an area...
We present a compact dual-modulus prescaler working at 50GHz without using inductors. A novel divider-by-2/3 in a reduced logic with minimum number of transistors is presented. For the first time, a single-phase clock digital-logic-based prescaler operating at frequencies in the mm-wave band is demonstrated. A power consumption of 130.2µW at 50GHz, gives the best power-efficiency reported. The prescaler...
A new low power divide-by-3 injection locked LC divider is proposed for PLL-based frequency synthesizers. The circuit is made of two voltage controlled oscillators coupled together via four MOSFETs, where capacitors are placed in series with the source of the coupling transistors leading to a reduction in power consumption. The control voltage of the two VCOs are tied together to achieve a wider locking...
We proposed a voltage-controlled oscillator (VCO) and an injection-locked frequency divider (ILFD) at a stacking topology. The proposed circuit has its optimized performance and low power consumption. The circuit was designed in a 0.13 µm CMOS technology. The VCO's output frequency is from 11.2 GHz to 13.4 GHz while the ILFD's output frequency is from 5.6 GHz to 6.7 GHz. The total power consumption...
Frequency dividers are one of the most significant blocks in Millimeter-wave communication systems and became a research hotspot in recent years. In this paper, an 8:1 static divider is implemented in 0.13-μm CMOS technology. The realized static divider achieved a measured performance of 34 GHz maximum operating frequency with 0 dBm input power and consumes 14.5 mA current from 1.2 V power supply...
An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current-mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive...
This paper describes the modeling and design considerations of a low-power divide-by-two injection-locked frequency divider (ILFD) for 60GHz frequency synthesizer applications implemented in 90nm CMOS process. The paper proposes a divider's locking range model based on mixing analysis. The design uses a capacitor bank for the divider band selection and tail current injection. Measured results of the...
The design of a 12 GHz Low-Power Extended True Single Phase Clock (E-TSPC) Prescaler is presented in this paper. First the function and advantages of the TSPC technique are explained. Examples of basic TSPC structures are given to clarify the functionality. Afterwards the design and implementation of the E-TSPC based Prescaler is shown. This static through-eight divider consists of three divide-by-two...
An ultra-low voltage operation of 0.5 V, 5-bit Flash ADC has been developed and achieved an ENOB of 4.2-bit at a conversion rate of 600 MS/s. It consumes only 1.2 mW and attained an ultra-low FoM of 160 fJ/conv. steps at an ERBW of 200 MHz. A forward body bias technique and gate-interpolated double-tail latched comparator with variable delay method to compensate the mismatch voltage are introduced.
A current-bleeding technique is presented to enhance and maximize the locking range of a differential-input Miller divider (MD) without extra inductor and extra power. The maximum locking range and the associated optimal bleeding current to achieve minimum required output amplitude are derived. Implemented in a 0.13μm CMOS technology and with 0dBm input power, the divider prototype measures...
Two millimeter-wave current mode logic (CML) flip-flop-based static frequency dividers, divide-by-4 and by-2, are realized in a 90nm bulk CMOS. In order to achieve a large locking range and a high operating speed, capacitive-bridged shunt peaking techniques are implemented by taking advantage of the parasitic capacitance. The first flip-flop in these two dividers can directly drive the second flip-flop...
A 60-GHz injection-locked frequency divider (ILFD) fabricated in 65nm CMOS and operating at 1.2V consumes 1.65mW excluding buffers and biasing circuits, and has a measured locking range of 48.5-62.9GHz (25.9%) with 0dBm input power. The core ILFD area is 0.0157mm2. The large locking range is attributed to the use of the multi-order LC oscillator topology.
This paper presents a low power glitch-free dual-modulus (15/16) prescaler based on the phase-switching for Ultra-Wide Band (UWB) transceiver. An inherently glitch-free phase-switching prescaler is realized by the adoption of a reverse switching sequence without any additional complicated circuit. A simplified model of the source coupled logic (SCL) structure is proposed to optimize the power of the...
In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-2/3 prescaler is investigated. Based on this analysis, a new ultra low power wide band 2/3 prescaler is proposed and implemented using a GlobalFoundries 0.18 μm CMOS technology. Compared with the existing E-TSPC architectures, the proposed 2/3...
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