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The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying...
A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit...
A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has...
The advent of dynamic CMOS logic, more precisely domino logic, made them widely used for the implementation of low power VLSI circuits. However, the main drawback of this logic is the non implementation of inverted logic. To implement the inverted logic, it is required to duplicate the logic circuit up to that part with inverted inputs. This obviously results the increase in area, delay as well as...
With the advent of battery operated devices and scaling trends in deep submicron (DSM) regime, leakage power is becoming large component of total power dissipation. In this paper leakage reduction techniques viz. Stack forcing and Multi-Threshold CMOS (MTCMOS) have been implemented on CMOS, Complementary Pass Transistor Logic (CPL), and Transmission Gate (TG) logic style based digital circuits. The...
An analysis of XOR gate designed using Gate Diffusion Input (GDI) technique is presented in this work. Comparative investigations are also carried out for XOR gates designed using conventional, low power as well as GDI techniques. SPICE simulations verify the results. The analysis shows that at 100MHz, circuit designed using GDI technique consumes 73.79%, 73.61%, and 46.64% less power compared to...
In this article, the main design tradeoffs in design of ultra-low-power (ULP) and robust digital systems will be discussed. Here, the goal is to explore the main tradeoffs among design parameters such as device sizes and supply voltage, and system parameters such as robustness and energy dissipation. This study provides the necessary basis for design optimization and comparing the conventional CMOS...
In Flash ADC designs, the speed of thermometer code to binary code encoder often becomes the bottleneck in achieving ultra high speed. This necessitates new design for encoder which can operate accurately at multi Giga hertz range. In this paper, a unique encoder design technique is presented which exploits the signal pattern in thermometer code and generates corresponding binary bits using lower...
XOR and XNOR gate plays an important role in digital systems including arithmetic and encryption circuits. This paper proposes a combination of XOR-XNOR gate using 6-transistors for low power applications. Comparison between a best existing XOR-XNOR have been done by simulating the proposed and other design using 65nm CMOS technology in Cadence environment. The simulation results demonstrate the delay,...
A general concern in VLSI design is power efficiency. It is indeed very obvious that battery operated equipment, such as handheld cellular phones, laptop computers etc. impose stringent limits on the acceptable power dissipation. The power dissipation of CMOS circuits is determined at different levels. On the system/architecture level, pipelining, replication, retiming, and bit-serial operation can...
Embedded memory is a critical component of modern SOCs. In highly scaled CMOS, process variability and device aging degradation cause a significant increase in the soft failure rate of embedded SRAMs. As process technology continues to scale, these issues become more pronounced, especially when the device is operating at its minimum operating voltage, VDD MIN. This failure rate can even exceed the...
Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. To improve switching performance, energy/switching, and also the robustness of the subthreshold logic for the implementation of 1-bit static full adder, we propose the use of sub-FinFET (sub-threshold voltage FinFET) transistors. The power, speed and energy evaluation has...
The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases...
In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These...
In the design of an ultra high speed Flash ADC, a major challenge lies in designing a high speed thermometer code to binary code encoder. In this paper, design of a high speed encoder deploying a new logic design style to convert the thermometer code to binary code with fewer transistors through the use of pseudo-dynamic CMOS logic circuits is presented. With this encoder a much higher conversion...
Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance...
Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit,...
In this paper, an integer linear programming (ILP) based algorithm is presented that considers resource constraints and optimize leakage delay product (LDP) using a precharacterized register transfer level (RTL) library. For nanoscale CMOS (nano-CMOS) circuits leakage is a predominate form of power dissipation. Leakage optimization at the early stage of design cycle, such as during high-level synthesis...
In this paper we present an architecture for nanowire layer in FPNI which is include switch boxes concept. The FPNI improves the Field-Programmable Gate Array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches which decreases both the area and power consumption of the circuit...
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