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Analog-to-Digital converters plays vital role in medical and signal processing applications. Normally low power ADC's were required for long term and battery operated applications. SAR ADC is best suited for low power, medium resolution and moderate speed applications. This paper presents a 10-bit low power SAR ADC which is simulated in 180nm CMOS technology. Based on literature survey, low power...
Pulse generator serves an important role in gated ring oscillator (GRO) based Time-to-Digital converters (TDC) to enable the ring oscillator for the input time difference between two reference timing events. As the resolution of TDC advances to a few picoseconds, the linearity of the pulse generator becomes increasingly important. This paper reviews and compare between pulse generators implemented...
The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information...
A single-stage hardware is scheduled for multiple operations, reset, offset cancellation, pre-amplification and latch. Applying multi-level voltage on gate terminal of the reset switch controls the strength of positive feedback devices and manages multiple operations. Also, with reliable control on positive feedback, a high-gain offset cancellation loop can be formed with no longer need to auxiliary...
A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.
We present the implementation and experimental verification of the first complete digital logic library based on amorphous carbon (a-C)-coated curved-cantilever nanoelectromechanical (NEM) switch technology. Experimental results for sequential gates - latches and edge-triggered D flip-flops (DFF) - and combinational circuits (NAND, AND) are reported for the first time. The capability of the fabricated...
We present the implementation and experimental verification of the first complete digital logic library based on amorphous carbon (a-C)-coated curved-cantilever nanoelectromechanical (NEM) switch technology. Experimental results for sequential gates - latches and edge-triggered D flip-flops (DFF) - and combinational circuits (NAND, AND) are reported for the first time. The capability of the fabricated...
Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified...
In this paper, a Linear Feedback Shift Register (LFSR), designed using MOS Current Mode Logic (MCML) is presented. Three different implementations of LFSR based on the three design methodologies of MCML D-Latch (D-Latch using traditional MCML style, D-Latch using switch-based MCML tri-state buffers and D-Latch using low power MCML tri state buffers) are realized. All simulations are performed in PSpice...
A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital Converter (ADC) that uses improved dynamic comparator has been introduced in this paper. In this improved dynamic comparator, a novel pre-amplifier is proposed in order to enhance the bandwidth up to 817 MHz when compared to classical pre-amplifier structures. Besides, a modified dynamic latch with driving simultaneously...
This paper presents a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The proposed switching detect logic can avoid switch power wasted and reduce the impact of capacitor mismatch from the layout parasitic as well as improve the resolution performance of SAR ADC. The ADC consumes 3 uW at 0.5-V supply and 1.28-MS/s sampling rate, achieves high ENOB and FOM...
The need to design and develop high performance and high speed VLSI systems such as NOCs in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. In such devices managing the power among the domains of a system is of real concern. Hence, the low power design techniques namely: clock gating, power gating,...
A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel...
This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters...
This paper proposes Flash Analog to Digital Converter design that reduces static nonlinearity of the track & hold circuit, by that high speed and high linearity obtained at the same time. Comparator is designed using latch type voltage sense amplifier. The sense amplifier is designed with separated input and regeneration stage. This separation offers fast operation over a wide common mode and...
This paper, deals with Latch Free Clock Gating technique for reduction of clock power and dynamic power consumption in ITC'99 bo1 Benchmark circuit and we have compared power reduction at different device operating frequencies. Without latch free clock gating technique in b01 benchmark circuit the Contribution of Clock power was 37.50%, 37.64%, 4.46%, 38.75% and 38.76% of total dynamic power when...
Serial communication facilitates the high-speed communication in gigascale systems. Serializer designs typically use the current-mode logic to achieve high speed at the cost of large power consumption. For the latches in the serializer, the power-hungry current-mode logic is replaced with differential cascaded pass-gate to reduce the power and delay. For the selectors in the serializer, the conventional...
This paper presents a new pseudorandom test pattern generator with preselected toggling (PRESTO) activity. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter and armed with a number of features that allows this device to produce binary sequences with low toggling (switching) rates while preserving test coverage...
Placement is considered a fundamental physical design problem in electronic design automation. It has been around so long that it is commonly viewed as a solved problem. However, placement is not just another design automation problem; placement quality is at the heart of design quality in terms of timing closure, routability, area, power and most importantly, time-to-market. Small improvements in...
Clock gating is one of the power-saving techniques used on the Pentium 4 processor and in next generation processors. To save power, clock gating refers to activating the clocks in a logic block only when there is work to be done. From the earliest days of the Pentium 4 processor design, power consumption was a concern. The clock gating concept isn't a new one; however, the Pentium 4 processor used...
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