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Most of the literature on image filtering using FPGAs focuses on the normal case when the window is completely within the image. The exception - when the window is partly off the edge of the image - is rarely considered. If not managed appropriately, handling these exceptions can take up more resources than the main operation. Efficient techniques are presented that manage the image borders by reusing...
In this paper, we propose an approach for detecting line segments in real-time by merging fixed-size short line segments. In many hardware systems, a Hough Transform has been used for detecting line segments. The Hough Transform is robust to noises, but it requires large memory space, and more space is required for images with higher resolution. Line detection is a primitive task which is frequently...
A multi-channel image superimposition system is designed in this paper. It can superimpose white-light image on infrared thermal image to generate mixture image. The system is realized on a FPGA chip and is mainly composed of multi-channel DMA controller and image superimposition module. Multi-channel DMA controller can realize data exchange between image superimpositon module and memory independent...
The H.264/AVC standard achieves much higher coding efficiency than previous video coding standards. Unfortunately mis comes with a cost in considerably increased complexity at the encoder mainly due to motion estimation. Therefore, various fast algorithms have been proposed for reducing computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose...
Nowadays, embedded vision systems have to face new hard requirements involved by modern applications: real-time processing of high resolution images issued by multiple image sensors. Recently, a new adaptable ring-based interconnection network on chip has been proposed. Based on adaptive datapath, it allows handling of multiple parallel pixel streams. In this paper, we present a new hierarchical memory...
Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component...
This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times...
Fractal Image Compression (FIC) is a lossy technique whose features are promising for computer systems with few resources, however, it has been ignored due to the large amount of operations needed to complete the codification. On the other hand, the development of VLSI technology allows for the creation of programmable devices with greater facilities, which not only offer a large gate density to program...
In this paper efficient hardware architecture for deblocking filter in H.264 is presented. A parallel filtering order is proposed without violating the standard, and the architecture is implemented in pipelined dataptah. With the parallel filtering order the vertical edges and horizontal edges can be processed simutaneously, and the filtering efficiency is improved. The memory is arranged and orgnized...
Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it...
The image foresting transform (IFT) is a general tool for the design of image processing operators based on dynamic programming. Silicon image forest transform (SIFT) is a fast 8-bit data architecture for IFT-based operators in FPGA. It can implement queue-based methods such as morphological reconstructions, watershed transforms, shape saliences, distance transforms, skeletonization, edge tracking,...
The watershed transformation is a popular image segmentation technique for gray scale images. In this paper, we describe an implementation method of a watershed algorithm based on connected components on FPGA. In the watershed algorithm based on connected components, regular memory accesses by raster scans and irregular memory accesses using FIFO and stack are repeated. The irregular memory accesses...
In order to realize fingerprint recognition system in real time environment, we describe in this paper signal controller to read fingerprint sensor generated in FPGA devices. Basically this signal is generated using state machine. The simulation result for behavioral simulation and signal generation read by logic analyzer are presented in this paper. Initialization and reading time for 76800 pixels...
A new lossy compression algorithm for RF ultrasound signals (A-scan) is presented, which stores only the largest variations of the original signal. The largest variation (LAVA) algorithm is a two-step, constant bit-rate (CBR) algorithm, using only simple addition/subtraction operations, which is very suitable for FPGA implementation. The algorithm is targeted for automated ultrasonic testing (AUT)...
This paper presents a novel application specific instruction set processor specialized for block motion estimation. The proposed architecture includes an efficient register file system in terms of data reuse and parallel processing. Performances and area costs are presented for different levels of parallelism and register file dimensions. Various FPGA implementations of the architecture are further...
In this paper, we present an efficient H.264 intra frame coder system that achieves real-time performance for portable consumer electronics applications with low hardware cost. The system includes a low cost intra prediction hardware design that implements all intra prediction modes used in H.264 video coding standard based on a novel organization of the intra prediction equations. The proposed hardware...
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