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This paper presents the design of an hybrid course-fine time to digital converter for low power applications. The core of the circuit consists of two current-mode SAR analog to digital converters working in a time-interleaved fashion. The TDC has been fully simulated at the transistor level with a 0.13-μm CMOS technology. The paper discusses the design details and the digital calibration techniques...
Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm...
This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multichannel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear DAC is implemented. The chip is fabricated in TSMC 130nm...
The current trend for intensive computational architectures is to adopt massive parallelism, with several concurrent tasks performed simultaneously, as done for example in GPUs. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. It has however evidenced an important bottleneck...
Electrical biosensors are one strategy being explored for the development of a rapid point-of-care and onsite DNA testing tools since this technology is amenable to miniaturization, can be accurate and highly sensitive with simple instrumentation, and relatively inexpensive. A label free and fully integrated semiconductor sensor array based on differential charge-based capacitance measurement for...
This paper presents a configurable SRAM for low voltage operation supporting both pseudo two-port SRAM (P2P-SRAM) and single-port SRAM (SP-SRAM) functions in one compiler. Unlike conventional pseudo two-port SRAM that always performs read first, this work enables dynamic read-or-write-first selection and write-through function. It can improve SP-SRAM function speed by 90% faster than that of the conventional...
We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic...
Optogenetic forms of retinal prosthesis promise higher resolutions and more precise neural coding than electronic implants. This is predicated on high resolution, high radiance optoelectronic illuminators. In this paper, we describe a 90×90 CMOS driven micro light emitting diode (LED) array. Our device is implemented on a 0.35 µm CMOS process combined with a dedicated technology Gallium Nitride LED...
Folding of analog signals is one of the most efficient techniques employed in digitization of high speed signals at intermediate resolution. However, its implementation is restricted by distortion resulting from limited bandwidth at the output of the folders, interpolation at the output and comparator offset. In this paper a method to increase input signal processing capabilities and reduce the number...
Multiplier is one of the primary hardware blocks in modern day digital signal processing (DSP) and communication systems. It is extensively used in DSP and image processing applications such as, Fast Fourier Transform (FFT), convolution, correlation, filtering and in ALU of microprocessors. Therefore, high speed, low area and power efficient multiplier design remain the critical factors for the overall...
Multipliers play a key role in today's digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets — high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various...
A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA), and 16 SAR ADC's. The chip includes (i) a programmable delay cell array to adjust the interleaved sampling phase, and (ii) a 12 Gbps low voltage differential signaling...
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to...
A 4-bit 65nm time-based analog-to-digital converter (ADC) targeting the next-generation Square Kilometre Array (SKA) is presented. This ADC is composed of an analog voltage-to-time converter (VTC) front end and a digital time-to-digital converter (TDC) back end. The two components can be physically separated to minimize the impact of digital noise from the ADC on high-gain, high-sensitivity receiver...
An 11b asynchronous successive approximation register analog to digital converter with embedded passive gain architecture is proposed and prototyped in 65nm CMOS. The proposed passive gain technique is integrated in the sampling capacitor network as part of the SAR conversion, and provides a signal gain of 2x prior to the comparator without consuming static current. It thus reduces the comparator...
This paper presents a 0.55 V, 7-bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, dynamic amplifiers with a common-mode detection technique are used as residual amplifiers to increase its robustness against supply voltage lowering. These amplifiers also remove the unnecessary static power consumption achieving clock-scalability in power performance. The 7-bit prototype ADC fabricated...
This paper proposes a mechanism for suppression of charge sharing in single photon processing pixel array by introducing additional circuit. The idea of the proposed mechanism is that in each pixel only analog part will introduced, the digital part is shared between each four pixels, this leads to reduce the number of transistors (area). By having communication pixels, a decision that which one of...
A new background calibration technique for correcting timing-skew mismatch errors in time-interleaved analog-to-digital converter (ADC) is reported. In this approach, the time derivative of the input signal is directly sampled and utilized for skew calibration. Reference ADC equalization is used in tandem to correct any static mismatch errors. Behavioral simulations show 26 dB and 44 dB improvement...
The design and measurements results of analog-to-digital converter implemented in CMOS 180 nm technology have been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications...
A low noise single-ended to differential linear two-stage switched capacitor variable gain amplifier (SC-VGA) is designed in a 0.18μm CMOS technology for 4MHz center frequency (fc) ultrasound imaging. To simplify the clock generator and improve linearity, the voltage sampling technique is adopted to replace the charge sampling for sake of the source impedance of piezo-electric transducers (PZT) not...
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