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Simplification of the hardware part of digital design adds complicity to the software tools. In addition, the details of physical hardware wiring, timing, and models' specifications are being illuminated in so many new versions of CAD software. This adds challenges for new designers especially for those in educational institutes. The issue of complex design tools has never been addressed in literature...
This work is related to System-On-A-Chip architectures and design methodologies, for cryptographic algorithms implementations. Alternative approaches are presented, for architecture and architectures for block ciphers, stream ciphers, and hash functions. The presented algorithms are the most wide used, in all certain of modern applications. Implementation aspects are given for both ASIC and FPGA integration...
The use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, Dynamic Partial Reconfiguration (DPR) is suitable to change this hardware logic when needed and while the rest of the system continues its functioning...
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
In his paper we attempt to give a networking solution by applying VLSI architecture techniques to router design for networking systems to provide intelligent control over the network. Networking routers today have limited input/output configurations, which we attempt to overcome by adopting bridging loops to reduce the latency and security concerns. Other techniques we explore include the use of multiple...
We present in this paper NOCEVE an industrial Network on Chip (NoC) emulation and verification environment on industrial large scale multi-FPGA emulation platform for billion cycle application. It helps designer to improve system performance by the analysis of traffic distribution and balance through the network on chip. The hardware monitoring network is generated by another commercial NoC design...
Due to the runtime flexibility of modern dynamically reconfigurable SRAM-based FPGAs, FPGA devices have become an attractive platform for developing system-on-chips (SoCs) for space applications (space SoCs). However, since the FPGA's SRAM is highly susceptible to space radiation, system reliability is a primary concern for space SoCs. To maintain system reliability and mitigate space radiation effects,...
The paper describes an experience of creating a hardware implementation of a pairwise sequence alignment algorithm in a high-level hardware description language. The implementation is created to be run on an FPGA with a high latency interface to a PC (ethernet). Thus, a lot of control logic is implemented in hardware together with the main pipeline. We use a HaSCoL hardware description language for...
The reuse of predefined Intellectual Property (IP) can shorten development times and help the designer to meet time-to-market requirements for embedded systems. Using FPGA IP in a proper way can also mitigate the component obsolescence problem. System migration between devices is unavoidable, especially for long lifetime embedded systems, so IP portability becomes an important issue for system maintenance...
The growing demands on multimedia applications and high-speed high-quality telecommunication systems with real-time constrains oriented to portable, low power consumption, devices, have being driven technologies development, methodologies and design flows of embedded systems during the last years. Through the analysis of design methodologies and strategies facing multi-core, reconfigurability and...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
This paper aims at introducing a methodology that allows an easy implementation of IP_Cores focusing only on their functionalities rather than their interfaces and their integration in a given architecture. The proposed approach implements all the communication infrastructure needed by a component described in VHDL, to be finally inserted into a real architecture that can be implemented on FPGAs,...
The Reconfigurable Data-Stream Hardware Software Architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core systems on a programmable chip. Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software or hardware, that communicate over a seamless interface....
This paper presents a novel pipelined architecture of the competitive learning (CL) algorithm with k-winners-take-all activation. The architecture employs a codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. An efficient pipeline architecture is then designed based on the codeword...
Network-on-Chip (NoC) is an important communication infrastructure for System-on-Chips (SoCs). Designing high performance NoCs with minimized area overhead is becoming a major technical challenge. In this paper, we propose the on-the-fly virtual channel (VC) allocation for low cost high performance on-chip routers. By performing the VC allocation based on the result of switch allocation, the dependency...
In this paper, a system for time-frequency analysis of heart rate variability (HRV) using a fast windowed Lomb periodogram is proposed. Time-frequency analysis of HRV is achieved through a de-normalized fast Lomb periodogram with a sliding window configuration. The Lomb time-frequency distribution (TFD) is suited for spectral analysis of unevenly spaced data and has been applied to the analysis of...
This paper presents a novel binary fully adaptable window for incorporating in a stereo matching System-on-Chip (SoC) architecture. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. For each window a binary mask window is generated which selects the supporting pixels in the cost aggregation phase of the SAD algorithm...
The communication latency of Network-on-Chip (NoC) is one of the factors that significantly impacts on the application performance on System-on-Chips. To reduce the NoC latency, we propose a low latency architecture of router, which utilizes virtual output queuing (VOQ) to shorten the processing time of a packet transfer. Based on taking advantage of VOQ in buffering, the number of pipeline stages...
Because the speed degradation and on-chip resources limit large CAM applications on SoCs and FPGAs, Hash-CAM architectures are attractive concepts combining the space efficiency of hashing algorithm and fast lookup character of the CAM for collision resolutions. In proposed Hash-CAM circuit, single and double hashing schemes are explored and compared. It proves that, with parallel CRC circuit and...
This paper proposes an FPGA-based System-on-Chip (SoC) architecture with support for dynamic runtime reconfiguration. The SoC is divided into two parts, the static embedded CPU sub-system and the dynamically reconfigurable part. An additional bus system connects the embedded CPU sub-system with modules within the dynamic area, offering a flexible way to communicate among all SoC components. This makes...
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