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Enabled by modern languages and retargetable compilers, software development is in a virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; but hardware development practices lag far behind. We hypothesize that existing hardware construction languages (HCLs) and novel hardware compiler frameworks (HCFs) can put hardware development on a similar evolutionary path...
This paper presents results on FPGA of a RISC-V based Application Specific Processor (ASP), used as the main classification unit for acoustic pattern recognition of firearms and chainsaws in environmentally protected areas. The classifier is based on the Hidden Markov Models (HMM) technique, giving a probabilistic estimation of the current state of an acoustic environment, thereby identifying particular...
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The...
Deep neural networks (DNNs) are widely used in data analytics, since they deliver state-of-the-art accuracies. Binarized neural networks (BNNs) are recently proposed optimized variant of DNNs. BNNs constraint network weight and/or neuron value to either +1 or −1, which is representable in 1 bit. This leads to dramatic algorithm efficiency improvement, due to reduction in the memory and computational...
This paper describes the RTL design and hardware characterization of 64 bit light weight block cipher TWINE-80. Twine-80 is an inherently small hardware design with lesser number of gates and low power consumption compared to many of its counterparts. Twine has 36 rounds which reduces the chance of attacks. Hardware prototyping of twine cipher is done on Spartane6 FPGA. Structure of Twine is simpler...
The increasing amount of network throughput and security threat makes intrusion detection a major research problem. In the literature, intrusion detection has been approached by either a hardware or software technique. This paper reviews and compares hardware based techniques that are commonly used in intrusion detection systems with a special emphasis on modern hardware platforms such as FPGA, GPU,...
Elliptic Curve Cryptography have known, in recent years, an increasing success in security applications thanks to their advantages such as a short keys size with a high security level. Their popularity has led to various implementations in terms of algorithms, curves, coordinate systems, platforms, etc. The aim of this work is first to explore actual trends of ECC-based implementations in different...
Characteristics of the known FFT module IP-cores as well as its basic building blocks were analyzed. The problem of creating a multiplatform HDL-description of the FFT-module for FPGA-based, semicustom or custom integrated circuits was identified. The approach to develop a universal HDL-description based on platform independent control unit and adopted to the platform main structural blocks was proposed.
Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers. In this research work, recently proposed 64 bit Secure Force (SF) algorithm is implemented on an FPGA based full loop-unroll architecture. The proposed FPGA implementation of Secure Force yields a throughput of 2.3 Gbps for encryption, 2.6 Gbps for decryption, and 3.43 Gbps...
Side channel attacks take advantage from the fact that the behavior of crypto implementations can be observed and provides hints that allow revealing keys. In this paper we present a novel approach to prevent SCA or at least to increase the effort to reveal keys significantly. Our approach is based on the fact that there are some functions used in cryptographic operations that can be implemented using...
A wide variety of maximum power point tracking (MPPT) algorithms for photovoltaic systems (PVS) have been proposed and developed. These MPPT algorithms vary in many aspects such as the selected criteria and techniques used. In this paper, we propose an effective design methodology for hardware implementation of PVS into FPGA/ASICs. To achieve our goal, we propose the application of the model based...
SMS4 is widely used in the Chinese National Standard for Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure), and in WLAN WAPI, low-cost and efficient cryptography algorithm implementation is necessary and challenging. This paper proposes an ultra-compact IP core architecture, where the input data is processed in bytes. The proposed architecture further reduces its hardware consumption...
Coordinate Rotation Digital Computer (CORDIC) algorithm is well known and widely used in many computer systems due to its simplicity and the variety of functions it provides. Although CORDIC is known to be able to work in several modes and coordinate to provide elementary functions including trigonometric and transcendental functions, most proposed CORDIC enhancement and application were only limited...
This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high-level synthesis methodology to RTL micro architecture. The process is guided with performance measurements...
Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an...
A novel information detection method has been proposed for a fast and efficient search engine. This method is implemented on hardware system using FPGA in advance for functional verification and then on ASIC using 0.18µm CMOS technology. We take advantages of Content Addressable Memory (CAM) which has an ability of parallel multi-match mode for designing the system. The system operates based on CAM...
The intension of this work is to design ASIC (Application Specific Integrated Circuit) for LFSRs (Linear feedback shift register) used in cryptography systems.(Stream ciphering). Presently FPGAs (Field Programmable Gate Array) and Processors are used for this purpose which have speed limitations. Since FPGAs have general structure and implementing LFSRs in FPGAs are unable to achieve the required...
This work is related to System-On-A-Chip architectures and design methodologies, for cryptographic algorithms implementations. Alternative approaches are presented, for architecture and architectures for block ciphers, stream ciphers, and hash functions. The presented algorithms are the most wide used, in all certain of modern applications. Implementation aspects are given for both ASIC and FPGA integration...
A new high-performance and reduced hardware architecture for the computation of the H.264/AVC forward and inverse quantization operations is presented in this paper. This architecture is based on a highly flexible processing structure that is suitable for very efficient implementations using both FPGA and ASIC technologies. Moreover, it offers several different configurations, in order to provide...
Artificial Neural Networks (ANN) find applications in various fields of science and engineering. The training of ANN is an iterative process which consumes huge amount of time when executed on conventional microprocessors. It can be accelerated by adopting parallel computation techniques. This paper presents a Verilog HDL based parallel Hardware Architecture for ANN training using Particle Swarm Optimization...
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