The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Field programmable gate array (FPGA) devices are increasingly being deployed in industrial environments, making reconfigurable hardware testing and reliability an active area of investigation. While FPGA devices can be tested exhaustively, the so-called application-dependent test (ADT) has emerged as an effective approach ensuring reduced testing efforts and improving the manufacturing yield since...
Modern digital circuits are, with each technological evolution, increasingly affected by Single Event Upsets (SEUs). In this paper we propose a static analysis approach for the estimation of the SEU sensitivity of the system under design by identifying untestable faults. The approach relies on a formal specification language to model circuits at the gate-level and on the Linear Temporal Logic (LTL)...
A new methodology for radiation induced real-time fault detection and diagnosis, utilizing FPGA-based architectures was developed. The methodology includes a full test platform to evaluate a circuit while under radiation and an algorithm to detect and diagnose fault locations within a circuit using Triple Design Triple Modular Redundancy (TDTMR). An analysis of the system was established using a fault...
In this paper we present a new software framework to analyze and modify circuits netlists in an automatic fashion. We developed an API that implements low-level functionalities above which it is possible to create complex algorithms. We then developed a second software layer to implement hardening techniques for Single Event Effects (SEEs) in digital microcircuits. Experimental results prove the effectiveness...
Various algorithms and testing schemes have been developed in the past for testing memories for the presence of faults. Due to the increasing popularity of FPGAs, some schemes have specifically been developed for testing memories in these devices. FPGAs, when used in airborne space applications, are exposed to radiations which can produce faults within their memory. Faults may also develop during...
This paper presents a built-in self-test (BIST) approach for testing configurable logic and memory resources in Xilinx Virtex FPGAs using hard-macro. The resources under test include the configurable logic blocks (CLBs) and block random access memories (BRAMs) in all of their modes of operation. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults of...
With the increased use of FPGA in widespread applications, its?? size and speed has been rapidly increased, so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault, but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality, so testing...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far....
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.