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The coarse-grained reconfigurable image stream processor (CRISP) architecture is introduced for the image processing demands of high-definition (HD) cameras and camcorders. With several architectural concepts of the reconfigurable architecture, the CRISP architecture is proposed to meet the performance and flexibility requirements of the HD cameras. A multi-frame processing system with CRISP is implemented...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
Computer architectures for advanced driver assistance systems have become increasingly important in the automotive industry. They target safety-critical applications, which process large amounts of incoming sensor data. This is especially the case for image processing applications, which must handle several uncompressed image streams from multiple cameras. As one possible target architecture, FPGAs...
This paper presents the implementation and evaluation of a computer vision task on a Field Programmable Gate Array (FPGA). As an experimental approach for an application-specific image-processing problem, it provides results about gained performance and precision compared with similar solutions on General Purpose Processor (GPP) architectures. The problem of detecting Binary Large OBjects (BLOBs)...
Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from photographs that capture reality for a short period of time. They are renewed and transmitted at a rate of 25-30 frames per second, in a typical real-time scenario. Each of these frames needs to be filtered and processed in order to detect a feature on it. This processing...
This paper presents an event-driven vision system, including a dual-line dynamic vision sensor and a general purpose address-event processor tailored for real-time and highspeed applications. The asynchronous and self-spiking pixels of the dynamic vision sensor are times tamped with high-precision and routed to the processor for flexible and data rate-dependent information processing. The general-purpose...
Embedded processors with fixed architecture have disadvantages: they are neither reusable nor are they flexible enough to match the specific needs of different application domains. The main technique employed to accelerate instruction execution in such processors is to add fixed hardware units, which may be useless for some applications yet insufficient for others. This additional hardware may affect...
The stable Euler-Number based image binarization gives excellent visual results for video frames containing high amount of image noise. Being computationally expensive, its implementations are limited to general purpose processors for the most cost-effective solution or in application specific integrated circuits for maximum performance. This paper proposes a modified stable Euler-number based algorithm...
Nowadays the real time video processing is becoming more and more critical. Thus the systems used for these purposes require powerful computation of the data in order to have short response time. Another attribute that is preferred for these systems to have, is versatility or offering the opportunity to be reconfigurable on demand. Co-design is a technique that involves both software and hardware...
Hand-held leaf area meter which measure leaf area rapidly, accurately and nondestructively is introduced. The microprocessor of leaf area meter is ARM9 microprocessor S3C2440. S3C2440 is the hardware core, which has external expanded mass memory, CMOS camera, LCD touch screen and other modules. Embedded operating system Windows CE is selected as operating system. Application is developed with EVC...
This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and for the configuration of the processor. The toolset enables the exploration of the processor's design space in order to find an optimal configuration depending on the target application. The use of the toolset to test different...
Nowadays, the advances in the semiconductor industry allow to include a considerable number of fully digital processing elements on a chip. These massively parallel processor arrays are already able to host cellular wave computing algorithms with acceptable time performance. In this paper we approach the implementation of an originally CNN based algorithm for retinal vessel tree extraction on the...
This intelligent analysis instrument is equipped TFT LCD as displaying terminal. First, timing and logic requirements of a typical TFT LCD are introduced. Hardware circuit between microprocessor S3C2410 and TFT LCD module are designed. Then, based on Windows CE, developing software driver code mainly focus on setting related registers of displaying interface and adjusting the position of displaying...
This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy...
The H.264/AVC Intra Frame Codec (i.e. all frames are coded as I-frames) targets high-resolution/high-end encoding applications (e.g. digital cinema and high quality archiving etc.), providing much better compression efficiency at lower computational complexity compared to MJPEG2000. Moreover, in case of video coding of very high motion scenes, the number of Intra Macroblocks is dominant. Intra Prediction...
Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. When building multichip mutilayered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b)...
Modern graphics cards are supported with powerful computational facilities for fast computation of vertex geometry and realistic rendering of 3D graphics. The introduction of programmable pipeline in the graphics processing units (GPU) has enabled configurability. GPU which is available in every computer has a tremendous feat of highly parallel SIMD processing, but its capability is often under-utilized...
A low complexity algorithm for post-processing deblocking and implementation with a configurable processor designed by us is presented in this paper. The algorithm is aimed at improving subjective visual effect and reducing the complexity for hardware design. According to the masking effect of human visual system (HVS), the blocking artifacts can be recognized only when the blocking artifacts continually...
High speed image and video processing is becoming increasingly important in many applications, especially in robotics. A high speed vision system involves grabbing image frames from a single or multiple sensors and processing of the data in a limited time. Therefore, the requirement of real-time processing of the images is the key problem in dealing with such applications. Moreover, to obtain the...
Fingerprint recognition is one of the most common techniques used for biometric identification. Currently fingerprint technology is suitable to recognize users with high accuracy and low execution times using microprocessors able to solve algorithms with high-computational cost. However, the microprocessorpsilas cost could make the use of fingerprint biometric conditional on specific applications...
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