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Nowadays, most of the cipher cryptographic technologies target on designing the algorithms which oppose an analytical attack by another third party intellectual property (3PIP) having access to cipher-text. In this regard, the physical security of cryptographic devices needs an immediate attention. Currently, due to the distributed functionality of the Integrated Circuit (IC) manufacturing industry,...
Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom...
With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of...
Precise control of synchronous drive depends on the accurate position feedback of the rotor. This can be achieved using an absolute position encoder. One of the protocol used for encoder is Synchronous Serial Interface. The encoder with this protocol has to be interfaced with the drive or the testing setup in laboratory. In order to avoid a physical hardware, this paper proposes the SSI protocol implementation...
This paper presents a distributed, real-time platform for aerospace power system design, testing and evaluation, which was developed by the University of Dayton, in partnership with GE Aviation's Electrical Power Integrated Systems Center (EPIS Center). This platform is based upon heterogeneous distributed, real-time computing hardware. Also, high-fidelity, physics-based or behavioral models can capture...
To improve the signal to noise ratio in the auto-tracking receiver, the traditional two dimensional acquisition algorithm is often used. However, its application has been limited because of the large amount of calculations. In this paper, a low-complexity cross-correlation algorithm is proposed. Firstly, the theoretical deviation is given. And then its implementation based on Field Programmable Gate...
Multicore GPU, Intel MIC, and FPGA supplemental parallel processors have become widely implemented in High Performance Computing Clusters (HPCCs). In HPCCs, Computing nodes are assembled with these supplemental processors for specific research applications, images are applied to do the research. Since HPCC computing nodes require completely different design configuration from one day to the next,...
The increasing need for high-performance dependable systems with and the ongoing strong cost pressure leads to the adoption of commercial off-the-shelf devices, even for safety critical applications. Ad hoc techniques must be studied and implemented to develop robust systems and to validate the design against all safety requirements. Nonetheless, white-box fault injection relies on the deep knowledge...
The very high levels of integration and submicron device sizes used in emerging VLSI systems and FPGAs lead to frequent occurrences of defects and operational faults. Thus, the need for fault tolerance and reliability of deployed systems becomes increasingly prominent. This paper discusses fault tolerance and reliability observed in the design of a parallel self-healing VLSI system, based on partial...
Reconfigurable systems based on Field-Programmable Gate Arrays (FPGAs) can offer performance and power advantages over processor-based systems as well as cost and flexibility advantages over custom integrated circuit solutions. Dynamic reconfiguration, the ability to partially modify a circuit implementation at run-time, has the potential to extend the flexibility, utilization, and resilience of FPGA-based...
Prime numbers testing algorithm was implemented in specialized digital hardware. The design was coded in VHDL, verified, synthesized and loaded into FPGA. In-house developed Ethernet interface was integrated to provide external control of the computing machine from a desktop computer. Address Resolution Protocol (ARP) was added to extend this connection beyond the local area network. The device may...
Long testing time, low efficiency and large volume are the major problems of the test system launcher equipment of one air defense missile, which is also one of the exclusive testing equipment. To address those issues, a new FPGA-based test system for launcher is proposed with corresponding framework of hardware and software , which is designed through the analysis of the test parameters and performing...
This paper proposes a high speed serial data acquisition scheme. The scheme adopts Nios II soft processor in FPGA instead of application of specific chips in digital system to realize and control serial data acquisition, and especially focuses on the hardware designment with Quartus II and software development with Nios II EDS. This design shortens the design processs, simplifies the circuits, and...
Large digital integrated circuits designed to solve space applications, have to be designed following standards that recommend to include hardening techniques against Single Event Phenomena caused by harsh radiation environments. It is specifically important in the case of modern deep-submicron technologies. Single Event Effects are phenomena related to the effects of radiation when ionizing particles...
This paper proposes a validation methodology for implementing solutions to challenges involved with power electronic converter design. Typically, the design process consists of first simulating the converter and then implementing it on hardware. Here, an intermediate step is added where the controller is connected to a real-time simulator before being connected to real hardware. This allows for virtual...
A novel modification of a cross-correlation algorithm has been designed and implemented as digital hardware process. The algorithm was written in Verilog and tested running on FPGA hardware at 100 MHz. The algorithm presented has a modular architecture that is fully scalable and can be used to correlate a large number of different length pseudo random binary sequences (PRBS). A real-world interface...
A need arises when using CAN buses to monitor the data on the bus as well as having the ability to inject further data onto it. This provides the ability to fully test a CAN network on both the frame level and the bit level. This paper introduces a new CAN bus analyzer and emulator. The proposed system on chip (SoC) is verified by simulation and implementation on FPGA board. Real time results show...
The automotive industry is now facing many problems and challenges that put many restrictions on car design, towards the minimization of the car cost. Most of the problems arise from the continuously increasing need to provide more advanced features in the modern cars. This lead to a dramatically increase in the percentage electronics inside the car, which lead to increasing the number of Electronic...
Hardware-in-the-loop (HiL) testing can be very expensive because of the high acquisition costs of the required hard- and software. In this paper an alternative low-cost realisation for building up a HiL testing system is introduced. This solution is based on a standard FPGA together with a normal desktop personal computer (PC). It will be shown that almost all of the required features of a HiL testing...
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