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Packages of commercial Gallium-Nitride power semiconductors present increasingly small dimensions to enable low parasitic inductance, increasing the heat flux density of the package and the challenges associated with their thermal management. This paper compares between Printed Circuit Boards and Direct Copper Bonded as substrates for a Gallium Nitride based half-bridge from a thermal and reliability...
Nanosilver paste has become a promising lead-free die-attach material for power electronic packaging. This development solves the challenges faced by power device manufacturers to replace the lead-based or lead-free solders for high-temperature applications. This paper proposes the reliability of a 1200-V/150-A multichip insulated-gate bipolar transistor (IGBT) module using pressureless sintering...
There are increasing interest in high temperature endurable sensor or device packaging solution for a set of wide ranging applications that include oil and gas production or deep sea exploration, advanced automotive application, aerospace, more electric aircraft initiative (MEA) or engine health management (EHM) systems, geothermal energy harvesting as well as other renewable energy industries. Besides...
Molded underfill (MUF) process for system in package with WLCSP package with cu pillar bump would be the future application in SIP module assembly due to small form factor and low cost of WLCSP and good electrical, thermal performance, fine pitch and lower cost of cu pillar bump. However, higher stiffness of cu pillar could cause interface fracture between cu pillar and solder bump during SMT process...
Advances in wide band-gap semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) offer many high temperature electronic applications. However, current packaging technologies hinder taking full advantages of the high temperature capabilities offered by these devices. This paper discusses the material and fabrication issues and technologies for high temperature packaging.
The trends towards miniaturization in the electronics industry coupled with advances in flip chip technology have increased the use of flip chip on board or direct chip attach technology in many products. This is especially true for products where re-work is not an option. Reliability issues were overcome by the use of underfill to couple the chip to the substrate and subsequently significant advances...
Flip-chip ball grid array (FCBGA) packaging was developed to meet the requirements of high I/O density and high electrical performance and the trend of persistent miniaturization of electronic products. Underfill is usually used in flip-chip packaging to fill the gap between the silicon die and the substrate to provide solder bumps protection, compensation of the coefficient of thermal expansion (CTE)...
A type of 3D-SiP (System in Package) package for wireless sensor network (WSN) node was designed and developed based on an embedded FR-4 substrate using 3D technology (including, embedded way and stacked way) and SiP technology. The 3D-SiP package including sensor (sound or vibration) module, baseband ASIC chips, digital signal processor (DSP) chips, other chips and various passive components, was...
The low coefficient of thermal expansion (CTE), high modulus and high glass transition temperature (Tg) underfills with silica filler have been successfully used for extending the thermal fatigue life of flip chip to package substrate interconnection. And along with the explosive growth of portable electronics market in recent years, various polymeric materials are also applied for reinforcing the...
High density interconnect (HDI) flip-chip ball grid arrays (FCBGA) substrate becoming more and more popular for high end applications, to meet greater number of I/O pads, increasing I/O pad density, higher operational frequencies and smaller package body size. Microvia in HDI substrate has much smaller scale comparing to conventional plated through-hole (PTH) substrate, which is prone to have microvia...
Thermal performance and reliability are necessary to be considered for high-power electronic packaging device design. In this paper, the thermal characteristic of one kind of packaging device was studied using FEM and experimentation, for phase shifter. The model for thermal condition of phase shifter was established. The top junction temperature obtained by simution shows tendency as tested experiment...
In a typical LED package module, a grease layer forms the interface between the substrate and copper heat spreader. We propose to carve grooves on the aluminum substrate to form an array of protruding posts. Three types of grooves are designed to measure interface thermal resistance. A preliminary feasibility study shows obvious improvement in the thermal resistance of the interfaces for the formation...
The drive for small form factor and foot print area packages is being fueled by consumer electronic applications that today constitute 50% of semiconductor revenue. Mobile phones are experiencing explosive growth both in terms of unit shipments and increased complexity at the same time. In just one decade mobile phone has transformed from a simple communication device into more complex system integrating...
In this paper an improved LED (Light emitting diode) packaging structure was proposed, which is based on COB (Chip On Board) technology. This research mainly analyzed the thermal reliability of a 4×4 square LED die array with COB technology during temperature load. Simple intuitive for observation, two specific red glue curing profiles were compared with different curing temperature, curing time,...
The advanced QFN (aQFN) package is an enhanced version of conventional QFN (Quad Flat No-Lead) with multiple row terminals of featuring higher number of I/O ports. aQFN thermal and electrical performance are superior due to smaller profile, shorter interconnects. Also, the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of...
The anti-pyramid stacked chips distribution that can be applied in SIP is reported to have a much better thermal performance comparing to the widely used pyramid distribution. When the package of system is using PCB and LTCC condition, the highest temperature is brought down from 440°K to 417°K and from 326°K to 319°K respectively. In addition, it is also analyzed that the anti-pyramid distribution...
In electronic product, reliability of solder joint has big impact on the function of the whole electronic product. In the design period of the package, it is important to predict solder joint thermal fatigue lifetime and analyze the effect of each factors on the lifetime of solder joint. Finite Element Analysis (FEA) based solder joint lifetime prediction method, which used Anand viscoplastic constitutive...
Because of Moore's (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch...
A new type of 3D multichip module (3D-MCM) for wireless sensor network was developed based on a kind of embedded FR-4 substrate for the wireless sensor network, in which FCOB (flip-chip on board), COB (chip on board), BGA (ball grid array) technologies, wirebonding and flip-chip interconnection technologies were combined together. The PBGA device and bare die were hybrid-integrated on the embedded...
With the demanding of market, the electronic portable products can be characterized by increasing signal frequencies and higher density of functions. The electronic products are expected to be produced smaller and smaller. There is one way to meet the requirement, which is a three- dimensional integration of components. A new concept of a packaging structure is proposed based on an embedded chip structure...
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