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Contemporary digital systems must be based on the “System-on-Chip — SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays), but the implementation of asynchronous interfaces (asynchronous wrapper — AW) constitutes a major drawback for this kind of devices...
This paper presents the 10 Gb/s Ethernet Phy Forward Error Correction (FEC) sub-layer novel VLSI structure with the following 2 ideas: one is the frame boundary detecting methodology and the other is the fast frame synchronous structure. The first method increases the frame synchronizing speed by fully optimizing the candidate start position shift algorithm to accelerate the frame synchronization...
For a time invariant system with finite possible events, the possible scenarios are defined by the relative delays between the events. For testing the system, all the nonredundant scenarios need to be generated and utilized. A simple random number generator is inefficient and generates redundant scenarios. In this work, we derive the non-redundant set of scenarios and then propose a method for generating...
An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS technology. The clock generator achieves a measured...
A low-jitter 300- to 800-MHz de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while maintaining a wide loop bandwidth. The clock skew problem is detrimental in the high speed applications, especially when the skew is longer than multi-cycles. The proposed generator was fabricated in a 0.18-μm CMOS process. The clock generator...
Wind turbines are rapidly increasing and some times are disconnected from the grid intentionally or inadvertently and continue to supply local loads. If it was decided to reconnect to the grid, some problems may happen. This paper deals with the reconnection of islanded wind turbines to the grid and proposes a new method to reduce the high current effects of reconnection. The new method is simple...
A multiple-bandwidth 12-bit pipelined analog to digital converter (ADC) with edge-combiner digital delay locked loop for self clock generation and embedded sample & hold (S/H) circuit is presented. The ADC circuit in the proposed design avoids external clock signal for sampling, by generating the clock from analog input signal for a wide range of frequency operation. The proposed design is capable...
This article introduced a design principles and implementation method of a high resolution programmable digital delay generator. It described the system's composition in hardware and software view. This system is composed of deserializer MAX3885, high-speed clock generator AD9517-1, DDR2 SDRAM, serializer and USB2.0 Controller. Paper described FPGA software design methods includes DDR2 SDRAM controller...
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed...
We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13 μm GL130SB (130 nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters...
Perfect Space-Time Codes (STC) are full-rate, full-diversity codes originally proposed for Multiple Input Multiple Output (MIMO) systems. Based on Cyclic Division Algebras (CDA), they have non-vanishing determinants and hence achieve the Diversity-Multiplexing Tradeoff (DMT). In addition, these codes have led to optimal distributed Space-Time Codes when applied in cooperative networks under the assumption...
The detection of small defects in an SRAM cell with our WL-pulse timing-margin measurement scheme has been demonstrated on a 90nm 2Mb SRAM. WL-width control with a high resolution of 24.1ps and a wide range improves the sensitivity of detection for delay and SNM variations with only a 0.6% area overhead, and statistical analysis makes possible the detection of small-delay defects that, in conventional...
Coherent sampling is required in ADC testing. Unlike production testing in which fractional frequency is available, only sampling clock of ADC is available for ADC Built-in Self-test (BIST). Triangular stimulus generator controlled by sampling clock of ADC cannot provide enough information because same voltages are sampled in every period. To carry out valid data acquisition, different voltages in...
In this paper a Globally-Asynchronous Locally-Synchronous (GALS) pipelined processor is implemented on synchronous commercial FPGAs. A simple pipelined accumulator-based processor is implemented as an example for a pipelined processor with varying stages' delays. A novel port controller is designed to ensure the proper operation of the pipeline under any distribution of stage delays. The results show...
A high-speed programmable counter for PLL clock generator is presented. Compared with conventional approach, the design serves as a post-scale counter and has advanced clock shift ability to provide programmable phase shifting and duty cycle. The proposed counter is used to implement continuous division factors 2-32 at high frequency in a 0.13??m low power CMOS process. A so called ??delay partition??...
Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the throughput reduction and synchronization failures introduced by the widely used pausible clocking scheme, and propose an optimized scheme for higher throughput and more reliable GALS design. The local clock generator is improved...
In this paper, we consider asynchronous two-way wireless relay networks with amplify-and-forward protocol (AF- TWRN), where the distributed space-time code (DSTC) is utilized without synchronization among relays to assist the communication between two terminals. We analyze the pairwise error probability (PEP) behavior of DSTC for AF-TWRN under frequency-selective channels. From our analysis, it is...
A methodology for implementing GALS design in conventional FPGAs using existing tools is presented. The goals were to define the minimal set of basic asynchronous components, to examine the methodology of their implementation and to establish the design constraints and limitations of such circuits. Simulation results confirm that GALS designs implemented using the Look-Up Table or the Flip-Flop with...
An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine...
An all-digital clock generator for dynamic frequency scaling is presented by using a cyclic clock multiplier. It realizes the fractional or multiplied output clock within four reference clock cycles. The frequency of the output clock can be programmed as Mfref/N (fref is the reference clock frequency, 1lesMles7, and 1lesNles8). It has been fabricated in a 0.18 um CMOS process. The measured rms jitter...
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