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In the nanometer era, the mismatch between the pre-silicon model and the post-silicon timing behavior is becoming severer. Therefore, it is necessary to validate timing with post-silicon data. We propose a method that estimates all the segment delays in the observed paths of a design from post-silicon path delay measurements. Our method is based on equality-constrained least squares methods, which...
Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient...
A novel phenomenological inverter delay model is presented. The model focuses on capturing the percentage delay change as a function of gate length change (i.e., bias) over a wide, practical range of input slews and output capacitances that are typically used in library characterization. The model is derived based on physical device equations with empirical fitting parameters for improved accuracy...
Statistical static timing analysis(SSTA) is an emerging technique that addresses increasing process variation effects on circuit behavior for designs at 65 nm and below. SSTA offers a number of advantages over traditional corner based static timing analysis(STA), most notably it provides a more realistic estimation of timing relative to actual silicon performance. Accurate statistical timing analysis...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
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