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Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core...
The number of connected Internet of Things (IoT) devices was about 8.9 billion in 2012 and it is statistically estimated to grow up to 50 billion devices in the beginning of 2020. The security of the IoT plays an important role in the correct and advantageous functionality of the interconnected devices. For efficiency considerations, some of the IoT data processing is optimal to be implemented in...
Most networking performance enhancements occur through specific static solutions, where the structure of the protocol stack remains unchanged. Instead, we focus on a flexible software and hardware co-design for the entire protocol stack. In this paper, we present EmbedNet, a System-on-Chip implementation of a flexible network architecture for the Future Internet, where parts of the protocol stack...
This paper presents the Hardware/Software (HW/SW) implementation of Scalar Multiplication (SM) for Elliptic Curve Cryptosystem (ECC) over prime field Fp At low level of abstraction, the SM execution is based on the Modular Addition Subtraction (MAS) and the Modular Multiplication (MM) operations. In this work, we propose the implementation of the SM as a Programmable System on Chip (PSoC), using the...
This paper deals with automatic low-power and low-memory reconfigurations of flexible MP-SoC embedded architectures. The goal is to allow run-time software/hardware reconfigurations of the system that should be adapted to its changeable environment. Software reconfigurations mean the addition/removal/update of OS tasks and hardware adaptations mean the activation/deactivation of a processor. The OS...
The era of multiprocessor system-on-chip (MPSoC) has brought a new challenge for modern electronic systems. Communication between IP cores and other peripheral in the MPSoC environment is becoming critical which will affect the performance. Network-on-Chip (NoC) is a promising solution for MPSoC communication limitation. Several NoC studies have been reported over the years but only a few discussed...
In this article, we describe the architecture of the industrial controllers supporting Industrial Ethernet for motion control systems. We targeted and analyzed PROFINET, EtherCAT, POWERLINK, and SERCOS III, and applied the proposed design derived from the analysis to a prototype of an EtherCAT master controller. We evaluated an FPGA prototype cooperating with a Geode processor (500 MHz) running standard...
Data traffic keeps increasing dramatically in the connected world and it pushes hard on evolution of IO technology. As technology progress, a simple and high-speed unified interconnect becomes practical to support many different protocols. Light Peak (LPK) is a high-bandwidth, inexpensive optical interconnect technology developed by Intel for this purpose. Also, to meet versatile and ever changing...
Recognizing the strategic importance of embedded computing for industry and society, the European Commission formed, together with industry, academia, and national governments, the European technology platform ARTEMIS (Advanced Research and Technology for Embedded Intelligence and Systems) in 2004. It is one goal of ARTEMIS to develop a cross-domain embedded system architecture, supported by design...
Hash functions form an important category of cryptography, which is widely used in a great number of protocols and security mechanisms. SHA-2 is the up to date NIST standard, but is going to be substituted in the near future with a new, modern one. NIST has selected the Second Round Candidates of the SHA-3 Competition. A year is allocated for the public review of these algorithms, and the Second SHA-3...
Unlike traditional SoC (System-on-chip) chip, multiprocessor chip that contains multiple independent processors, each processor owns different applications, so we need to make a reasonable multiprocessor chip initialization program. This paper proposes a design for the multiprocessor system initialization. The main contribution is as follows: Firstly, one method for the implementation of multiprocessor...
While the computational core is becoming faster and faster, the communication efficiency between the processors has become a bottleneck which limits the performance of multiprocessor system-on-chip (MPSoC). This paper focuses on design and implementation of AXI bus protocol-based MPSoC architecture. Firstly, the RTL models of 4 NIOS II processors using AXI communication architecture are developed...
This paper presents a reconfigurable architecture for the session initiation protocol (SIP). SIP is a protocol used primarily to establish point-to-point sessions between users for multimedia communication. Furthermore it increases the performance of Internet applications and overall efficiency. However, most existing SIP solutions are entirely software based. SIP performance can be enhanced by executing...
Many FPGAs are served as network devices today. The ability of networked reconfiguration of such devices can enable the control and upgrading of them from a long distance. Previous researches on networked reconfiguration focused on hardware implementation of network protocols, neglecting there configuration integrity and security. This paper analyzed potential threats to reconfiguration integrity...
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