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Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. Usually, top-down methodologies are proposed, that start...
One of the newest computational technologies is the high performance heterogeneous computer (HPHC) wherein dissimilar computational devices such as general purpose processors, graphics processors, field programmable gate arrays (FPGAs), etc., are used within a single platform to obtain a computational speedup. Jackson State University has a state-of-art HPHC cluster (an SRC-7), which contains traditional...
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. The feature allows multiple...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
Implementing an algorithm to hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated to a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, because...
We present a reconfigurable architecture that can perform highly parallel regular expression matching. The system can be configured on programmable devices such as FPGAs as a set of instances of a predefined core called REMA. Each core addresses one of the subtasks into which the regular expression matching problem can be partitioned. These cores work in parallel on the same string analyzing different...
Reconfigurable network hardware makes it easier to experiment with and prototype high-speed networking systems. However, these devices are still relatively hard to program; for example, requiring users to develop in Verilog or VHDL. Further, these devices are commonly designed to work with software on a host computer, requiring the co-development of these hardware and software components. We address...
Hardware acceleration uses hardware to perform some software functions faster than it is possible on a processor. This paper proposes to optimize hardware acceleration using path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. These techniques are applied to the MIPS-to-Verilog (M2V) compiler, which translates blocks of MIPS machine code into...
This paper describes a design of a reconfigurable computing platform (RCP) based on the Intel Xeon general purpose processor and the Nallatech BenNUEY-PCI-4E field programmable gate array (FPGA) motherboard. The RCP is built to allow users with little or no knowledge of hardware design to program high performance computing applications that utilizes FPGA as the coprocessor. The RCP utilizes Impulse...
The hArtes -holistic approach to reconfigurable real time embedded systems- design flow addresses the development of an holistic tool-chain for reconfigurable heterogeneous platforms. The entire tool-chain consists of three phases: algorithm exploration and translation, design space exploration and system synthesis. This paper evaluates the tools in the design space exploration phase and the system...
We will explore how processing power of LEON3 processor can be enhanced by connecting small commercially available embedded FPGA (eFPGA) IP with the processor. We will analyze integration of eFPGA with LEON3 in two ways, inside the processor pipeline and as a co-processor. The enhanced processing power helps to reduce dynamic power consumption by Dynamic Frequency Scaling. More computational power...
Many practical algorithms require support for hierarchy and parallelism. Hierarchy assumes an opportunity to activate one sub-algorithm from another and parallelism enables different sub-algorithms to be executed at the same time. The paper presents a graphical specification of parallel hierarchical algorithms, suggests architecture of a parallel reconfigurable controller, indicates limitations and...
Many reconfigurable hardware architectures have been proposed so far, ranging from FPGAs to coarse grained architectures. Reconfigurability can be intended in several ways, and a number of diverse solutions have been proposed. One of the most relevant issues that have emerged is that the performance gain offered by reconfigurable hardware is balanced by relevant difficulties in their programming,...
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