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One of the consequence of the scaling down of latest technologies, is that digital circuits are more prone to be affected by faults caused by physical manufacturing defects, environmental perturbations (e.g., radiations, electromagnetic interference), or aging-related phenomena. Understanding the behavior of the whole system in the presence of faults affecting digital circuits is crucial for designing...
Serial based FPGA fault emulation schemes for probabilistic errors rely on a random number generator -- which is used for generation of fault bits - and a shift register - used for placing the fault bits to their corresponding fault location. It has two advantages with respect to parallel solutions: lower cost and better accuracy. The main disadvantage is represented by the high emulation overhead:...
This paper presents a new method for locating multiple faults in an interconnect following application testing of an FPGA. This method utilizes conditions related to the interconnect structure and in particular, the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. They yield to a rather adaptive approach by which faults are hierarchically...
This paper describes a Built-In Self-Test (BIST) approach designed to verify the integrity of the embedded multiplier cores in Altera Cyclone II Field Programmable Gate Arrays (FPGAs). This approach uses an architecture independent test algorithm implemented with parameterized VHDL to support all FPGAs in the Cyclone II family. The BIST is capable of detecting faults within all of the multiplier's...
This paper is the second part of a series of two papers addressing a hybrid framework for achieving fault detection, classification, and location, simultaneously. The proposed framework is formed by a variety of analysis techniques, including symmetrical component analysis, wavelet transforms, principal component analysis, support vector machines, and adaptive structure neural networks. In our previous...
This paper presents a fast fuzzy algorithm, implemented using field-programmable gate array (FPGA) to detect the stator related faults in induction motors. Altera Cyclone III FPGA was employed for developing the proposed method. All coding of fuzzy algorithm was written using hardware description language (HDL) called very high speed integrated circuit description language (VHDL). Fuzzy system has...
Fault isolation in automated test pattern generation (ATPG) / scan-fault has been increasingly challenging in today's advanced integrated circuit (IC) as diagnosis results usually point to extensive faulty nets which can be physically widespread on the die. This work highlights a novel approach in understanding electrical fault data with promising physical failure analysis (PFA) results in FPGA/ASIC...
As FPGA sizes and densities grow, their manufacturing yields decrease. This work looks toward reclaiming some of this lost yield. Several previous works have suggested fault aware CAD tools for intelligently routing around faults. In this work we evaluate such an approach quantitatively with respect to some standard benchmarks. We also quantify the trade-offs between performance and fault tolerance...
This paper presents the initial results obtained from a newly developed FPGA based traveling wave fault recorder installed on a medium voltage (MV) distribution line. The recorder is capable of recording six input signals, simultaneously sampling at 40 mega samples per second (MSPS) and at 14 bit resolution. It uses high bandwidth 17 MHz Rogowski coils connected to the secondary of a current transformer...
Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for...
This paper presents a newly developed, FPGA based, travelling wave fault recorder capable of simultaneously recording up to six input channels at 40 Mega samples per second (MSPS) at a 14 bit resolution. The fault recorder integrates a GPS receiver to provide accurate time tagging of recorded transients allowing both double-ended and single-ended schemes of fault location to be applied.
The abundance of configurable logic elements and routing resources in recent Field-Programmable Gate Arrays (FPGAs) provides a cost-effective method for tolerating permanent faults in the system. Once a permanent fault occurs, the FPGA can be reconfigured by replacing the faulty part with previously unused resources in the same hardware. In this paper, we present two column-based precompiled configuration...
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