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Based on two-port measurements, a distributed compact model and an extraction method for the power bus of a high-speed memory chip are proposed. The 1-D model is constructed according to the relative locations of the power and ground pads on the chip. The power bus around each power or ground pad is modeled by a section of resistor-inductor-capacitor (RLC) T-model, and the complete distributed model...
A study of the substrate current was presented for a PD-SOI MOSFET under forward substrate bias. The substrate current is almost independent of the gate voltage and is dominated by the SSJ diffusion current for a bias above ~0.6V. BSIMSOI agrees only qualitatively with SENTAURUS simulations, and the model for the SSJ diffusion current must be reviewed in order to quantify accurately the substrate...
A new proposal of applying surrogate-modeling in input-output buffer information specification (IBIS) is presented. It saves the IBIS data storage resource, extends the model utility to various process-voltage-temperature (PVT) simulations and eliminates the data interpolation deviations.
This paper presents an approach for building new compact macromodels of differential output drivers. Composed of enhanced physical-based elements, the new models are capable of capturing the important intrinsic nonlinear and dynamic characteristics of the drivers. We demonstrate the approach with two typical digital drivers, low-voltage differential signaling (LVDS) driver and pre-emphasis driver...
To improve prediction accuracy of die yield, a novel fuzzy neural networks (FNN) based yield prediction approach is proposed. The yield prediction model is built, in which the impact factors of yield, including physical parameters, electrical test parameters and wafer defect parameters are considered simultaneously and are taken as independent variables. A back-propagation algorithm is used to train...
The implementation of a feasible circuital solution for modeling complex systems as STAR cellular neural networks requires circuits with features and performances tailored for the specific application. In particular, this paper deals with the design of a current mode digitally programmable non-linearity that has been properly developed for a "time-division architecture" implementation of...
The scaling of supply voltages and the increased level of integration have conspired to make the analysis and design of microelectronic systems increasingly challenging. The impact of dynamic noise due to signal switching, die-package coupling, power management techniques, substrate coupling, etc., can been seen at all levels of a power delivery network, from chip to package to mother board to the...
Verification plays more and more important role in complex VLSI design. It has two main challenges: one is to insure that the input stimulus can control the function spots inside the design; the other is to insure the errors can be observed from the design output. This paper presents an easy approach of assertion-based verification (ABV) method by dividing it into five steps, through which we embed...
Thermal management is becoming a major concern in microelectronics because of transistor technology reduction and power density increases within complex packages. Temperature rise due to power dissipation worsens harmful clock skew, jeopardizes reliability and leads to over-consumption because of leakage current dependence on temperature. To limit these risks, electronics engineers have to perform...
The scope of this article is concerning the electrical modeling tools used for the package parasitic extraction. Many 3D electrical modeling tools are on the market today enabling different type of electrical models to represent the electrical behavior of the packages. Semi-conductor companies are using many of them to address a wide range of applications, going from Communications, Consumer and Computer...
Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy VDD waveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some errors may exist in the simulation. In this paper,...
In this paper, CAD models of the input admittance of RC interconnects are discussed. To this aim, properties of RC circuits are exploited to show that the input admittance of RC wires is approximated very well by that of a low order RC circuit, as opposite to the timing modeling of RC wires. In particular, 1st- or 2nd-order equivalent circuits are shown to be sufficient for fast and accurate estimations...
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