The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A recent trend in the electronics industry is the concept of intelligent wearables and the Internet of Things (IoT) such as smart watches, fitness trackers, smart sensors, and smart glasses. Low power consumption is a requirement of the processors and the increasingly large embedded SRAMs in such devices. Lowering the operating voltage of these devices makes them low power. However, process variation...
Phase transition materials (PTM) [1] have shown an immense promise for several applications such as realizing steep switching Phase-FETs [1], augmenting the read operation of memories [2-3], non-linear selectors for cross-point memory arrays [4] and in the design of neurons [5] and oscillators [6]. Their unique properties open up new avenues for other designs as well and therefore, there is a need...
The design and analysis of a low power comparator that features an offset cancellation technique has been carried out in this paper. The proposed low power circuit works on a 1 GHz sampling frequency and is developed in 65nm CMOS technology. An offset cancellation technique and a switch are added to the comparator to reduce the offset and kickback noise. The comparator is implemented in a 5-bit Flash...
In this paper, a variation-aware simulation framework is introduced for hybrid circuits comprising MOS transistors and spintronic devices (e.g., magnetic tunnel junction-MTJ). The simulation framework is based on one-time characterization via micromagnetic multi-domain simulations, as opposed to most of existing frameworks based on single-domain analysis. As further distinctive capability, stochastic...
Recently, methods for switch network generation have gain relevance. The main goal of these techniques is to minimize the number of transistors in the logical arrangement. However, theses methods do not consider optimizations at layout level. In this paper, we propose a post-processing technique in a state-of-art method for network generation to improve some layout aspects such as area, delay, power...
To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application...
Multiple independent-gate field effect transistors (MIGFETs) have great potential for digital integrated circuits. In this work, we demonstrate that conventional binary adder architectures may benefit from the use of MIGFET devices. As case studies, we have designed ripple-carry adders (RCA) and parallel-prefix adders (PPA), where circuit area and performance optimizations are explored. Different...
This paper presents Subthreshold Design of Schmitt trigger logic gates for low power operation by using Variable Threshold CMOS Technique (VTCMOS).The proposed design of Schmitt trigger are form on buffer design using dynamic threshold MOS (DTMOS) for better low power operation. By improving the Schmitt trigger to AND/OR/XOR Gates, with minimum switching power consumption as well as area reduction...
A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated...
This paper presents a low-power automatic supply multiplexer for reconfigurable step-up/down switching DC-DC converters. The multiplexer continuously compares the input and the output voltages. It then tracks and selects the higher voltage to be used for substrate biasing and supplying gate drivers. This reduces leakage current through substrate diodes and also reduces conduction losses of the driven...
In this paper we present a current mode saw-tooth folding amplifier with a minimal number of current mirrors in the signal path from input to output. This minimizes the delays imposed by current mirrors on the speed of the amplifier. The amplifier has a full scale delay of 5.9ns which is more than four times faster than presented in previous literature. The operation is verified in simulation using...
Whereas buffers significantly impact Network-on-Chip (NoC) performance, they also account for up to 75% and nearly 50% of NoC router area and power respectively. Traditionally, SRAM has been used as an area and power efficient implementation of the router buffer. However, motivated by the smaller size and lower-power potential of planar embedded DRAM (eDRAM), we implement the router buffer using a...
In most of the multimedia applications such as audio, speech, graphics and video the final output is interpreted by human senses, which are insensitive to small errors. So, it is not required to produce exact numerical outputs. Considering the advantage of relaxation in numerical accuracy, this paper propose several approximate multipliers for error tolerant applications which are designed by using...
A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a...
The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers...
Current-controlled oscillators (CCO) for analog to digital conversion need linear tuning-characteristics. A new CCO design in which the period of oscillation is defined by charging the timing capacitor to a reference voltage by the input current, is described. The sources of non-linearity in the tuning characteristics are identified and modeled. A method of compensating for these errors is presented...
This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm...
This paper compares classical CMOS versus Schmitt trigger (ST) inverters (INVs), sized both conventionally as well as unconventionally. The reason is that ST INVs are using positive feedback (which leads to hysteresis) and are expected to exhibit much better static noise margins (SNMs) than classical CMOS INVs. That is why ST INVs are more reliable. Lately, quite a few papers have been looking at...
A high-voltage high-speed gate driver to enable synchronous rectifiers with zero-voltage-switching (ZVS) operation is presented in this paper. A capacitive-coupled level-shifter (CCLS) is developed to achieve negligible propagation delay and static current consumption. With only 1 off-chip capacitor, the proposed gate driver possesses strong driving capability and requires no external floating supply...
Serial communication facilitates the high-speed communication in gigascale systems. Serializer designs typically use the current-mode logic to achieve high speed at the cost of large power consumption. For the latches in the serializer, the power-hungry current-mode logic is replaced with differential cascaded pass-gate to reduce the power and delay. For the selectors in the serializer, the conventional...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.