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Size scaling CMOS transistors are known to improve cost, speed, and power per chip that results in high performance IC. However, too small transistor size can degrade transistor performance thus become limitation to CMOS scaling. One way to overcome this limitation is by incorporating CMOS with memristor; a device that offers small size, low power, nonvolatile characteristic with switching ability...
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality...
This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power...
This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated...
In this paper the design of a voltage-mode switching mode amplifier in a 65-nm CMOS process in the GHz range is described. The amplifier can be operated with a rectangular drive signal with 50 % duty cycle up to 4 GHz and pseudo random bit sequences up to 4 GBit/s. The calibrated broadband PAE of the amplifier chip is 22 % at 2 GHz, 13 % at 3 GHz and 7 % at 4 GHz for a rectangular drive signal with...
In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was...
This paper presents a hybrid design based, CMOS millimeter-wave (mm-wave) single-polar single-throw (SPST) switch. The circuit design starts from the analysis and optimization of a distributed structure, while implemented using coupled lump elements for performance improvement and area-efficient layout. Moreover, a specific bias scheme is used to further decrease insertion loss by more than 0.5 dB...
In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits, operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential non-linearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/−0.0600 LSB and 0.0397/−0.1142...
With increasing contribution of leakage in total active power, run-time leakage control techniques are becoming extremely important. The Pass-Transistor Logic (PTL) is a better way to implement circuits designed for low power applications. As the technology is growing pass transistor logic has gained the prominent importance. In this design of 1 bit ALU, PTL technology has been deliberately implemented...
In this paper, a novel Direct Digital Frequency Synthesizer (DDFS) based on using non-uniform segmentation in sine-weighted Digital-to-Analog Convertor (DAC) is proposed. To generating beyond Nyquist frequency signal, parallel DACs with Return-To-Zero (RTZ) technique are used. In conventional DDFSs for generating signal, a Phase to Sine Mapper (PSM) is used that often includes a look-up table memory...
A low-cost silicon-based high efficiency CMOS-LDMOS switch-mode power amplifier (SMPA) line-up operating for sub-1GHz application is presented. The switch-mode operated LDMOS device is driven by high-speed, high voltage driver, implemented in a standard 0.14µm CMOS process technology. The CMOS driver uses high voltage extended-drain devices and delivers a 5.0VPP output voltage swing up to 1GHz. The...
As the transistor dimension keeps shrinking following trend predicted by Moore's Law, the voltage that transistor can sustain reliably is also reducing. For certain serial interface protocols (like the ubiquitous Universal Serial Bus (USB)) and some legacy input/output interfaces, high voltages like 1.8V, 3.3V and even 5.0V are still being used for protocol compliance. It is costly in silicon fabrication...
A design of low-power voltage detector (VD) based on current comparison technology is presented. This VD samples the power supply voltage and converts the sampled voltage to a current which will be compared with a reference. The current comparison technology simplifies the design without use of the resistor string and voltage comparators, and thus reduces the core area. The VD detects three thresholds...
Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar...
The work proposes a novel design of an Operational Amplifier which uses an Adaptive biased Differential Amplifier stage for biasing. When Operational Amplifier is configured as a Buffer, the output signal gets distorted even at low frequencies and it does not follow the input signal. To resolve this issue the designers need to go for alternative biasing schemes. On the other hand, when the Operational...
A 7GHz-clock 1mV-input-resolution comparator is designed and simulated in a 65nm CMOS process. The comparator offset is compensated by changing the body voltages of the input differential triple-well NFET transistor pair. A reset switch is added between two regeneration nodes to further match voltages in reset phase. Kickback noise in this comparator is reduced by isolating regeneration nodes of the...
Optimum Power gating sleep transistor design and implementation are critical to a successful low-power design. The large magnitude of supply and ground bounces, which arise from power mode transitions in large power gating structures results in wrong functioning of the circuit. We propose a novel power gating technique showing the trade-off between wake-up time and supply noise. This technique is...
This paper presents an open loop high speed CMOS sample and hold with improved linearity. Previously, an open-loop S/H and a method of charge injection cancellation were introduced [1]. However, it requires many clock phases. In this paper a new charge injection cancellation scheme has been introduced with improved linearity than the previous one while its implementation is simpler. The proposed S/H...
The AC power supply clocked circuits is a class of digital gates which uses clock signals replacing the VDD and ground terminals in the static gates. In this paper the guideline for an AC-clocked logic gate is described. One crucial problem related to digital circuits design is the zero-order calculation or first guess on the device dimensions. The DCVSL-Differential Cascode Voltage Switching Logic...
The paper gives short overview of an efficient CMOS technology based current source realization and layout design. The current source output will be shortened square wave signal [1],[2] and [3]. The output current value can be selected from range 5 to 100μA. The current source layout design needs good matching, the geometry and temperature influence has been analyzed and the optimal geometrical structure...
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