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The Network on-Chip (NoC) is considered as an emerging technology for distributed embedded systems which is proposed as an alternative interconnection solution in Mutli-Processors System on-Chip (MPSoC). This paper proposes a graphical toll that allows researchers to generate and configure quickly their Network on-Chip in the hope to evaluate easily their contributions in no time. Unlike major existing...
In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is...
In the past few years, Network on chip (NoC) is presented as the best communication architecture for complex chip. Unlike conventional bus, NoC allows many cores to communicate concurrently, provides more scalability and enhance the system performances. For this reason, we propose a flexible router for NoC architecture. The proposed router implements a minimal routing algorithm to avoid deadlocks...
Network-on-Chip(NoC) has been well accepted for energy efficient on-chip communications for many-core systems. As the technology scaling drives the number of cores upward designers of the on-chip interconnect for many-cores chips are facing with the dilemma of meeting performance and energy requirements with power and thermal constraints. This paper focuses on the Network-On-Chip energy and performance...
High performance computing are useful in performing colossal amount of computation. Interconnect network is crucial when such a tremendous calculation is happening. In order to perform high speed computation, nodes in the system must be connected with a high speed interconnection network. HPC systems have computation and communication parts and performance is limited by communication network rather...
The k-ary n-cube, or k-ary n-dimensional torus, is widely used as the interconnection network for constructing commercial supercomputers. Compared to the hypercube, torus has the advantage of ease of implementation but its diameter increases rapidly as the network scales up. This paper investigates the configurations of the k-ary n-cube by adjusting the parameters k and n according to the network...
Early design space exploration has been shown to be an important factor in reducing the development time for Network on Chips. In this paper, we present a Matlab toolbox aimed at the early-stage design space exploration for NoC router design, the router founding element of a NoC. The toolbox is based on the discrete event simulation engine SimEvents. The presented toolbox can be used to graphically...
Along with continuing advancement of network and chip technology, vast amount of new router designs will be designed and utilized in differentiated Internet-connected systems, on-chip interconnection in SoC, and evolving software-defined networks. In this research, from an analysis of current and future router designs, we observe that router designs share a common composition structure. We thus devised...
The systems of interconnection play a major role in the performance expected by System on chip (SoC). With the evolution of technology, conventional shared-bus based interconnections are no longer the ideal solution for the future SoC. Therefore Network on chip (NoC) is emerging as a perfect solution to enhance the communication structures for future SoC. Compared with the conventional interconnection...
Network on Chips (NoCs) has now replaced the bus based architectures for communication between different cores in a multiprocessor System on Chip (SoC). NoC integrates SoCs in a better manner. It has the advantage of good scalability and high bandwidth. The communication on NoC is carried out by means of routers. Routers are the back bone of NoC. The design of routers is different for different topologies...
Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC). By the developments achieved in integrated circuits (IC) manufacturing there have been attempts to design vast amounts of network on the chips in order to achieve more efficient and optimized chips. A better routing algorithm can enhance the performance of NoC. XY routing algorithm is a distributed...
We have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our method, a memory is shared between multiple physical links by using the multi-port memory. We evaluate and discuss the communication performance in the various situations. It is shown that the minimum number of memory banks required in multiport memory for 2D-torus and 2D-mesh networks is 8. Our proposed...
The link aggregation (LAG) technique for networks-on-chip (NoC) is described and investigated in the paper. It is shown that LAG permits to improve considerably the NoC saturation threshold due to connection of neighboring routers with the aid of multiple physical links. The proposed work has three main contributions. The first is the description of a structure and principle of operation of a NoC...
Network-on-Chip (NoC) is believed to be a solution to the existing and future interconnection problems in highly complex chips. Different alternatives proposed circuit-switched NoCs to guarantee performance and Quality-of-Service (QoS) parameters for Systems-on-Chips (SoC). However, implementing scheduling mechanisms with different service classes and exploring the advantages of wormhole routing and...
This paper reports on an investigation into bit-rate adjustment on high capability metro and core routers. The bit-rate is controlled in response to traffic load using EWMA (Exponential Weighted Moving Average), with parameters set to minimize the performance impact of the adjustments. The purpose of the adjustment is to enable energy savings. Our calculations show that 22.5% power saving is achievable...
As a result of the higher speed of bandwidth communication link, routing forwarding node is drawing us more attention. IP switching technology has been approved on the basis of the various analysis of the IP switching technology. We can get the three-layer IP routing technology system, which can bring us the shorter interval while transmitting dates and enhance the stability to support the transition...
The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how...
With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
This paper presents a router structure for Network-on-Chips called Quad Router which benefits from communication locality. The router can be shared among more than one Processing Element (PE), so the average hop count of a packet is decreased. This structure consists of eight input buffers and eight output ports by which two different topologies are introduced called Double-Link Mesh (DLM) and Crossbar...
With the increasing number of processor cores in chip multi-processors (CMPs), 2D Mesh has been gaining wide acceptance for inter-core on-chip communication. Program performance is more sensitive to the router latency than to the link bandwidth. This paper presents a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead...
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