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Hardware Trojan (HT) is one of the well known hardware security issue in research community in last one decade. HT research is mainly focused on HT detection, HT defense and designing novel HT's. HT's are inserted by an adversary for leaking secret data, denial of service attacks etc. Trojan benchmark circuits for processors, cryptography and communication protocols from Trust-hub are widely used...
FPGA based product development companies need third party IP cores to complete the product design time effectively and cost effectively. The one-time payment upfront licensing of IP cores is impractical for FPGA based products, which does not benefit either IP core vendors or product engineering companies. There is a need for good competitive pricing scheme which benefit product development companies...
This paper presents a comparison of throughputand end-to-end latency of synchronous and asynchronous heterogeneousNoC under uniform and exponential traffic conditionsusing different parameters. The parameters we have chosen areno. of cores, load (traffic) and no. of VCs of a router. Further, sinkbandwidth analysis of synchronous and asynchronous NoC underuniform traffic was studied and compared. The...
This paper investigates the various aspects of network on Chip(NoC) design and its FPGA implementation. A parametric approach of evaluating the FPGA resources, delay and maximum frequency of operation for a NoC design has been described which may help the designer to take early decision related to NoC designing and prototyping. Virtual channel(VC), flit buffer depth and flit data width are taken as...
Multiprocessor System-on-Chip platforms are gaining prominence in the field of SoC design, which accommodates several large heterogeneous semiconductor intellectual property (IP) blocks, integrated onto a single chip. However, there's a crisis of global interconnection with existing bus architectures in such SoC Designs. In response to this crisis, Network-on-Chip (NoC) is an upcoming paradigm, and...
Control area network (CAN) is a two-wired, half duplex, high-speed network system that is far superior to conventional serial communication protocol such as RS232 in terms of functionality and reliability. CAN implementation are also cost effective. All CAN controllers in a network operate at the same frequency for safe and proper data transfer. As CAN uses Non Return to Zero (NRZ) bit encoding, long...
Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC). By the developments achieved in integrated circuits (IC) manufacturing there have been attempts to design vast amounts of network on the chips in order to achieve more efficient and optimized chips. A better routing algorithm can enhance the performance of NoC. XY routing algorithm is a distributed...
Direct Digital Synthesizers (DDSs) or Numerically Controlled Oscillators (NCOs) are nowadays prominently used in the applications of RF signal processing, satellite communications, etc. This paper brings out the FPGA implementation of one such DDS which has quadrature outputs. The proposed design, which is based on pipelined CORDIC, has considerable improvement in terms of spurious free dynamic range...
With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are...
This paper presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures...
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