The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a technique to improve the output swing of the charge pump (CP) block is introduced. CPs are one of the important building blocks of phase-locked loops (PLLs) and PLL-based clock and data recovery (CDR) systems. The proposed feedback-based approach ensures that the currents of the two current sources in the CP maintain their values over an extended range of the charge-pump output voltage...
This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference...
In conventional CMOS charge pump circuits, there are some non-ideal effects such as the clock feedthrough, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump to reduce the jitter. The proposed and conventional charge pumps are simulated and compared. The circuit is implemented using a 0.35??m mix-signal CMOS process...
A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1 MHz and settles in less than 180 ??s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.