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The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2...
In this paper, a technique to improve the output swing of the charge pump (CP) block is introduced. CPs are one of the important building blocks of phase-locked loops (PLLs) and PLL-based clock and data recovery (CDR) systems. The proposed feedback-based approach ensures that the currents of the two current sources in the CP maintain their values over an extended range of the charge-pump output voltage...
In this paper, an RF power harvesting system with automatic input tuning for long-range RFID tags is described. The system uses a high quality factor LC-matching network to boost the voltage of the received RF signal. Then a new high-efficiency voltage rectifier is used to extract DC voltage from the signal. In order to maximize the voltage gain of the matching circuit, a tuning loop automatically...
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