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A 14bit MDAC with 120MS/s conversion rate, in 0.35um CMOS technology is presented. The MDAC consumes a power of 36mW from a 3.3v power supply and its settling time is 7ns. It utilizes a new high speed, high gain Op Amp, with 102dB gain, and 1.2GHz bandwidth. The phase margin of Op Amp is 51° and its settling time is 5ns for feedback gain of 8. The Op Amp has a good linearity of -60dB.
A radix-3, 4-trits, Ternary Successive Approximation Analog to Digital Converter (TSAR-ADC), with an option to extend to radix-N approaches is presented. Proposed TSAR-ADC architecture generates 4 ternary outputs spanning 34 = 81 binary levels linearly for a rail-to-rail input voltage ranging from 0 to 3.3V. The radix-3 TSAR-ADC takes only 4 clock cycles for producing 4-trits or 6.33 bits in comparison...
This paper describes a readout channel suitable for infrared and terahertz bolometric sensors arrays where the signal integration is performed simultaneously with the analog-to-digital conversion in a columnwise architecture. By exploiting the need of an integrator both in conventional IR readout channels and incremental converters, the proposed circuit implements a 5-bit continuous-time incremental...
Low power, small volume and high acquisition precision are always important in the internal module of wireless implantable neural recording system. This paper describes the design and implementation of a new successive approximation (SAR) ADC to meet the unique requirements of wireless implantable neural recording system. In the designed new ADC, a fully differential structure is used to avoid the...
A 10-bit 3 Ms/s 90 nm CMOS SAR A/D converter is presented in this paper. Pseudo-differential comparison architecture is utilized to improve the performance, where the errors caused by clock feed-through and charge injection can be considered as common-mode interferences. Instead of traditional voltage scaling architecture, an R-C combination based D/A converter is used to reduce the chip area. And...
A 12b 2 MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3 Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1 mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18 mum CMOS technology demonstrates the effective number of bits of 11.48 for...
Time constant control (TCC) incorporating on-chip digital self-calibration technique performs two-step calibration of pipeline ADC stage errors and reduces power consumption at the same time. Using the proposed technique, the current of the amplifier in 1st pipeline stage employing TCC is reduced by 93%. The prototype 3.3 V 16 b 10 MS/s ADC based on 65 nm CMOS process is implemented in an active die...
A compact converter from capacitance to pulse width, suitable for interfacing integrated capacitive sensors is described. The circuit has been designed and fabricated using 0.32 mum/ 3.3 V CMOS devices from the BCD6s process of STMicroelectroncs and occupies an area of 1025 times 515 mum2. Measurements performed on the test chip showed an excellent linearity, a temperature drift of 300 ppm/degC, and...
A 40 MSample/s, 10-bit, 3.3V pipeline ADC is presented. In order to achieve very low power consumption, it employs a high bandwidth low-power amplifiers technique and a low power low offset dynamic comparators technique. The ADC is designed in 0.35 mum CMOS technology and occupies 1.2*0.8 mm2.
An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640times480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise...
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