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The demand for higher quality video has increased in the past few years, due to the huge amount of electronic devices that process digital video in even higher resolutions. For that purpose, video coding techniques are used, which have, as main goal, the reduction of the required representation to process a digital video. Furthermore, embedded hardware video solutions are sought for both industry...
Energy efficiency has become a primary concern in the design of multimedia digital systems, particularly when targeting mobile devices. Approximate computing is a highly promising approach to address this challenge. This paper presents an architectural exploration in a variable block size motion estimation (VBSME) architecture using imprecise Lower-Part-OR Adders (LOA). These adders were applied to...
The scalable extension (SHVC) of the High Efficiency Video Coding (HEVC) allows encoding in layers a video with multiple quality level such as resolution, bit-depth or Signal to Noise Ratio (SNR). Compared to the equivalent HEVC simulcast, the SHVC extension provides inter-layer prediction mechanisms enabling significant bit-rate savings. Moreover these inter-layer prediction mechanisms are less complex...
This work gives an efficient integer coefficient based discrete cosine transform (I-DCT) module architecture of different sizes that can be incorporated in favor of high efficiency video coding (HEVC) benchmark. This formation is optimized in terms of power and area. It is accompanied by a quantization block. Optimized constant matrix multiplication scheme is adapted to implement the I-DCT architectures...
The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures...
The main reason for the long time and high energy requirements of state-of-the-art Video Coding (VC) standards, such as the HEVC, is the large amount of distortion calculations. Among the most known and used ones is the Sum of Squared Differences (SSD) which has a strong correlation with the Peak Signal-to-Noise Ratio (PSNR). Such correlation is explored by current encoders to provide a good trade-off...
This paper proposes a flexible and efficient implementation of the 2D $N$ -point discrete cosine transform (DCT) for the High Efficiency Video Coding (HEVC) standard. The DCT is implemented through the Walsh–Hadamard transform (WHT) followed by Givens rotations. This scheme is exploited to derive an adaptive algorithm, which allows computing of four different approximations ranging from the complete...
In order to enable a system which offers compatibility with currently existing H.264/AVC based systems, 3D functionality, and a low overall bitrate, a multiview H.264/HEVC hybrid architecture was proposed in the context of 3D applications and standardization. This paper presents an algorithm to reduce the complexity of this multiview hybrid architecture by reducing the encoding complexity of the HEVC...
This paper presents a highly parallel motion estimation architecture for High Efficiency Video Coding (HEVC) encoder. The proposed architecture has 16 processing units operating in parallel to calculate the sum of absolute difference values of all possible variable prediction block sizes. Hence, it calculates the bit cost regarding every partition in order to find the best matching candidate in terms...
There are numerous video compression format for storage or transmission of digital video content. High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 Advanced Video Coding (AVC), that was jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265. In this...
A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of...
Transformation and quantization in block based video codecs introduces blocking artifacts at edges. Special optimized video filter called de-blocking filter is applied on 4×4/8×8 block boundary to enhance visual quality and improve prediction efficiency. Most of the recent video codecs, H.264, H.265 (HEVC), VC-1 uses in-loop de-blocking (LPF) filter in decoder path. Each video codec standard defines...
Motion estimation (ME) in video coding standard H.264/AVC adopts variable block size (VBSME) which provides high compression rates but requires much higher computation compared to the previous coding standards. To overcome this complexity, this paper describes a VHDL design and an implementation of VBSME. The design is based on partitioning each 16×16 macroblock into sixteen 4×4 non overlapping subblocks...
This paper presents design and implementation of a high throughput interpolator for the fractional motion estimation in HEVC systems. Novel data reusing scheme and highly parallel architecture are proposed such that timing efficiency and thus processing throughput of the system are enhanced. The detailed circuit architecture and timing analysis for the proposed interpolator will be given. Moreover,...
In this paper, we propose an optimized hardware architecture for the implementation of intra prediction in High Efficiency Video Coding standard (HEVC) decoder developed by the Joint Collaborative Team on Video Coding (JCT-VC) which is the common group released by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. HEVC is designed to achieve better coding efficiency...
High Efficiency Video Coding (HEVC) is new video coding standard beyond H.264/AVC. In this paper, an area and throughput efficient 2-D IDCT/IDST VLSI architecture for HEVC standard is presented. Adopting proposed data flow scheduling and shared constant multiplication structure, the architecture supports variable block size IDCT from 4×4 to 32×32 pixels as well as 4×4 pels IDST. Using 65nm technology,...
In hardware video encoders, the quantization and dequantization modules can consume a significant amount of hardware resources. This paper presents optimization methods for FPGA architectures of the modules. The methods allow a better utilization of resources available in DSP units and the reduction of general-purpose logic elements. Different versions of architectures are developed for FPGA Altera...
Nowadays, higher resolutions and faster processing time are more and more demanded in the field of video applications. Thus, algorithmic complexity of the encoder and its performances are the main penalties for such requirements. Recent woks show the efficiency of using the Multiprocessor System on Chip (MPSoC) technology to overcome the shortcomings of real-time processing with a single processor...
This paper presents a compression analysis about the High Efficiency Video Coding (HEVC) standard targeting a computational effort reduction at the scope of the motion estimation (ME). Restricting the Prediction Units (PUs) — among a total of 24 sizes — to the 4 square-shaped sizes in the HEVC interframes prediction, it is possible to reduce in 74% the number of operations at the cost of 4% increase...
This work investigates the trade-offs between energy and quality in video coding when pel decimation is applied. Realistic estimates for area and energy per block were obtained by simulating five different architectures specially designed to compute the Sum of Absolute Differences (SAD) for 4×4 pixel blocks. Among these architectures, one can be configured to operate with 1:1, 4:3, 2:1 or 4:1 sample...
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