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Nowadays, the amount of small devices performing any kind of Digital Signal Processing (DSP) has increased drastically. On the other hand, the limited energy available to such battery-powered devices is a real problem. In DSP applications, one of the most important operations is the Finite Impulse Response (FIR) filter computation. The main FIR filter characteristics are the linear phase and feed...
In FFT computation, the butterflies play a central role, since they allow the calculation of complex terms. Therefore, the optimization of the butterfly can contribute for the power reduction in FFT architectures. In this paper we exploit different addition schemes in order to improve the efficiency of 16 bit-width radix-2 and radix-4 FFT butterflies. Combinations of simultaneous addition of three...
Sum of Absolute Differences (SAD) is an intensive time-consuming operation of state-of-art video encoders. It is used as a block matching metric inside Motion Estimation (ME) and also on mode decision in Intra Prediction. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. Due to the simplicity, the SAD metric is the better...
The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures...
This paper addresses the reordering of coefficients, i.e., twiddle factors in multicore FFT in order to obtain power efficient datapaths. The coefficients are divided in smaller ones into the different cores and they are reordered through the Improved Anedma heuristic-based algorithm. According to the characteristics of the FFT algorithms, which involve multiplications of input data with appropriate...
This paper addresses the design of efficient 2's complement 64-bit array multipliers. We propose the combination of radix-2m dedicated multiplier blocks and adder compressors that leads to the reduction of partial product lines, and hence to the higher performance and least power consumption. The flexibility of the architecture allows for the easy construction of multipliers for different values of...
This paper addresses the exploration of different heuristic algorithms for a better manipulation of twiddle factors of Fast Fourier Transform (FFT). The FFT algorithm involve multiplications of input data with appropriate coefficients, hence the best ordering of those operations can contribute for reducing the switching activity, what leads to the minimization of power consumption in FFTs. The heuristic...
This paper addresses the exploration of different heuristic-based algorithms for a better manipulation of coefficients in Fast Fourier Transform (FFT). Due to the characteristics of the FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations can contribute for the reduction of the switching activity, what leads to the minimization...
This paper presents fast architectures for the forward and inverse transforms of the H.264/AVC video compression standard. These transforms can be computed exactly as in integer arithmetic, thus avoiding mismatch problems between the encoder and decoder. They are inserted into the T and T−1 block of the H.264/AVC and they can be computed by using only additions and shifts. Since the transforms algorithms...
The focus of this work is the improvement of performance of the encoder of the H.264/AVC by exploiting different architectural alternatives for the Forward 4×4 Hadamard Transform. This transform module is present in the critical path for the video compression that uses intra-frame encoding in H.264/AVC standard. Combinational and sequential architectures are proposed for the calculation of the Hadamard...
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