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In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of MHz, and in several cases exceeding the GHz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international...
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage (ABV) modulation and zero cross-regulation (CR) operation is proposed in this paper. To achieve the advanced power supply function in system-on-a-chip (SoC), the N-type low-dropout LDO regulator (N-LDR) is placed behind the SIDO converter to suppress voltage ripple and to eliminate the CR problem of SIDO converter...
In this paper we propose a fine-grain Adaptive Voltage and Frequency Scaling (LAVFS) architecture to optimize energy efficiency in presence of in-die variability. For each System-on-Chip power domain, we use a Dynamic Voltage Scaling technique called ‘Vdd-Hopping’ as efficient as DC/DC power converters but much easier to integrate and control at fine-grain. Unlike previous AVS schemes, the supply...
This paper explores the concept of developing a bondpad-less fully-integrated inductive link for power/data transfer between a CMOS Integrated Circuit (IC) and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35 µm process and occupies an area of 2.5mm×2.5mm and an on-chip inductor occupies an area of 1.5mm×1.5mm. At 900MHz,...
We look into the validation a power managed ARM Cortex A-8 core used in SoCs targeted for mobile segment. Low Power design techniques used on the chip include clock gating, voltage scaling, and power gating. We focus on the verification challenges faced in designing the processor core including RTL modeling of power switches, isolation, and level-shifting cells, simulation of voltage ramps, generation...
Aiming to SoC (System-on-Chip) power supply in portable devices, a high-conversion-ratio buck regulator is proposed. The operation duty cycle is expanded to 100% due to the emulated current mode. The 2.5 V to 4.5 V input voltage range makes it ideally suited for single cell Li-Ion battery supplied devices. The range of output voltage is from 1.2 V to input voltage accord to different kinds of SoC...
This paper proposes a resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. It has small area penalty because we use sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18μm CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively...
A hybrid voltage regulator module for an on-chip DC-DC voltage converter is proposed in this paper. The circuit is appropriate for point-of-load voltage regulation due to an ultra area efficient architecture. The proposed voltage regulator is a hybrid combination of a switching DC-DC voltage converter and a low-dropout regulator exploiting active circuitry rather than bulky passive devices within...
This paper presents a power supply module (PSM) for SoCs (system on chip). This module, which is based on an improved LDO, has a wide input range and switchable power path. The proposed PSM can output a steady voltage of 6v as input voltage varies between 5.7 V-30 V, with a max error of 4.3%. It also provides a flexible power path. The SoCs will be supplied by either internal LDO or external power...
As new functionality is added to the implantable devices, their power requirements also increase. Such power requirements make it hard for keeping such implants operational for long periods by non-rechargeable batteries. This result in a need for frequent surgeries to replace these batteries. Rechargeable batteries can satisfy the long-term power requirements of these new functions. To minimize the...
The design of integrated circuits, especially system-on-chips (SoC) is now constrained by many parameters such as speed, energy but also the robustness to process variability. Indeed, controlling the speed and the energy in a complex SoCs - which adopt the globally asynchronous locally synchronous (GALS) paradigm - require specific power supplies and clock generators as actuators and dedicated sensors...
This paper deals with the design of power supply distribution network in CMOS System-on-Chips to reduce electromagnetic emissions. The main sources of both conducted and radiated emissions are pointed out and the most popular solutions for these problems are summarized. Based on that, the paper shows a new power supply network and grounding scheme that strongly mitigate the off-chip propagation of...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44%voltage drop with about 10 % area overhead in a 65 nm CMOS. This DVB method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology.
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