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Codenamed “Zen”, AMD's next-generation, high-performance ×86 core targets server, desktop, and mobile client applications. Utilizing Global Foundries' energy-efficient 14nm LPP FinFET process, the 44mm2 Zen core complex unit (CCX) has 1.4B transistors and contains a shared 8MB L3 cache and four cores (Fig. 3.2.7). The 7mm2 Zen core contains a dedicated 0.5MB L2 cache, 32KB L1 data cache, and 64KB...
This paper explores microarchitecture controlled proactive gain boosting as a means of lowering the effects of supply voltage droop in digital circuits powered by embedded, all-digital linear regulators. A behavioral power supply rejection model for all-digital linear regulator is presented. The presented regulator shows enhanced power supply rejection under increased operating frequency. Test-chip...
This paper compares the impact of power supply variation on the performance of register-based and latch-based digital circuits. A 32-tap, 16-bit FIR filter is fabricated using both flip-flops and latches in a 130nm CMOS process. Measurements show 25–37% improvement in energy-efficiency for the latch-based implementation operating below 0.6V subject to 44–120mV, 1 kHz peak-peak VDD ripple. This paper...
Envelope tracking (ET) applications demand high tracking bandwidth and high efficiency using a DC-DC converter. Design based on small-signal models using fixed frequency digital pulse width modulator (DPWM) often results in limited closed-loop bandwidth. This paper proposes a mixed-signal hysteresis current control (MSHCC) in a DC-DC buck converter with an analog current-loop and a digital voltage...
This paper proposes an active resonant power supply noise cancelling with fast voltage drop sensor using the combination of delay-locked loop (DLL) and vernier time-to-digital converter (TDC). Also, we propose the capacitor selector circuit realizing the active insertion of capacitors in less silicon area. These components enable one clock noise detection with fine resolution. Simulation results show...
Charge pump circuits are currently becoming a realistic alternative to the switching regulators in high voltage generation applications, especially in fully integrated circuit systems. This paper discusses several stabilization methods to improve voltage performance and robustness of integrated high voltage charge pumps. All the discussion and measurements are based on a monolithic integrated high...
This paper is the third in a series of papers reporting on the results of protecting the microcontroller executed code against side attacks. The protection consists in randomizing, under the control of a chaotic circuit, of both the clock and the power supply voltage of a microcontroller. The results obtained by this double randomization are compared with the ones obtained with either clock or power...
In this paper we propose a fine-grain Adaptive Voltage and Frequency Scaling (LAVFS) architecture to optimize energy efficiency in presence of in-die variability. For each System-on-Chip power domain, we use a Dynamic Voltage Scaling technique called ‘Vdd-Hopping’ as efficient as DC/DC power converters but much easier to integrate and control at fine-grain. Unlike previous AVS schemes, the supply...
We look into the validation a power managed ARM Cortex A-8 core used in SoCs targeted for mobile segment. Low Power design techniques used on the chip include clock gating, voltage scaling, and power gating. We focus on the verification challenges faced in designing the processor core including RTL modeling of power switches, isolation, and level-shifting cells, simulation of voltage ramps, generation...
It has been demonstrated that dynamic voltage and frequency scaling (DVFS) leads to a considerable saving in dynamic and static power of a processor. In this paper, we present an adaptive framework that can be used to dynamically adjust supply voltage and frequency of a processor under different application workloads. Voltage scaling decisions are made by a fuzzy logic (FL) block based on variations...
The design of integrated circuits, especially system-on-chips (SoC) is now constrained by many parameters such as speed, energy but also the robustness to process variability. Indeed, controlling the speed and the energy in a complex SoCs - which adopt the globally asynchronous locally synchronous (GALS) paradigm - require specific power supplies and clock generators as actuators and dedicated sensors...
To decrease the power consumption of a switching power supply, the most effective approach is to lower the switching frequency. Hence, the current mode pulse-width-modulation (PWM) controller used in a switching regulator must be capable of frequency modulation at light-load condition. The green mode circuit is designed in proposed current mode PWM control IC with the concept of off-time modulation...
DVS (dynamic voltage scaling) is a technique used for reducing the power consumption of digital circuits. The power consumed by these circuits has a main component (dynamic power) that is proportional to the square of the supply voltage. Additionally, for every supply voltage, there is a maximum value of the clock frequency. The advantage of using DVS is that the supply voltage (and hence clock frequency)...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
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